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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
Content
1 2 3 SIS630 Overview .....................................................................................................1 1.1 Function Block Reference Table................................................................3 Features..................................................................................................................5 Pin Assignment......................................................................................................12 3.1 Pin Assignment (Top View).....................................................................12 3.1.1 SIS630 Pin Assignment (Top View-Left Side) ...................................12 3.1.2 SIS630 Pin Assignment (Top View-Right Side).................................13 3.2 SIS630 Alphabetical Pin List ...................................................................14 3.3 Power Plane..........................................................................................20 3.4 Muxpin ..................................................................................................21 Pin Description (Preliminary) ..................................................................................23 4.1 Host Bus Interface .................................................................................23 4.2 DRAM Controller....................................................................................27 4.3 PCI Interface .........................................................................................27 4.4 PCI IDE Interface...................................................................................32 4.5 VGA Interface........................................................................................33 4.6 Power management Interface.................................................................36 4.7 SMBus Interface ....................................................................................37 4.8 Keyboard controller Interface..................................................................38 4.9 LPC Interface ........................................................................................39 4.10 RTC Interface ........................................................................................39 4.11 AC' 97 interface......................................................................................40 4.12 Fast Ethernet and Homenetworking interface ..........................................41 4.13 USB interface ........................................................................................43 4.14 Legacy I/o and Miscellaneous Signals .....................................................44 4.15 Power and Ground Signals .....................................................................44 Hardware Trap.......................................................................................................46 Function Description ..............................................................................................49 6.1 MA Mapping Table .................................................................................49 6.1.1 SDRAM/System Memory................................................................49 6.1.2 SDRAM/FBC .................................................................................50 6.1.3 VCM/System Memory ....................................................................51 6.1.4 VCM/FBC......................................................................................54 6.2 PSON# and ACPILED Description ..........................................................55 6.2.1 ACPI.............................................................................................57 6.3 Power States for SIS630 Signals.............................................................58 6.4 Arbiter Tree ...........................................................................................62 6.5 Nand Tree Test Scheme.........................................................................63 Register Summary / Description - Core Logic..........................................................67 7.1 Device 0, Function 0 ( Host-to-PCI Bridge) ..............................................67 7.1.1 Configuration Space Header...........................................................67 7.1.2 Registers for Host & DRAM ............................................................68 7.1.3 Shadow RAM & PCI-Hole Area.......................................................69 i
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Hardware-Trap Control...................................................................69 Host Bridge & PCI Arbiter Characteristics........................................69 Clock Control.................................................................................70 GART and Page Table Registers ....................................................70 Integrated VGA Control ..................................................................70 A.G.P. ...........................................................................................70 7.2 Device 2, Function 0 (Virtual PCI-to-PCI Bridge) ...................................71 7.3 Register Description -- Core logic ...........................................................72 7.3.1 Host Bridge Registers (Function 0)..................................................72 7.3.2 Configuration Space Header .........................................................72 7.3.3 Host Control Registers ...................................................................77 7.3.4 DRAM Control Registers ................................................................78 7.3.5 Shadow RAM Area .......................................................................96 7.3.6 PCI Hole Area...............................................................................99 7.3.7 Hardware-Trap Control ............................................................... 101 7.3.8 A.G.P. GART and Page Table Control Registers.......................... 110 7.3.9 DRAM Priority Timer Control Register ........................................... 114 7.3.10 A.G.P. Control Registers ............................................................. 116 7.4 Virtual PCI-to-PCI Bridge Registers (Device 2).................................... 117 PCI IDE Configuration Space Register .................................................................. 125 8.1 Offset Registers for PCI Bus Master IDE Control Registers..................... 138 Register Summary / Description - Graphics........................................................... 142 9.1 General Registers................................................................................ 142 9.1.1 Miscellaneous Output Registers.................................................... 142 9.2 CRT Controller Registers...................................................................... 144 9.3 Sequencer Registers............................................................................ 152 9.4 Graphics Controller Registers ............................................................... 155 9.5 Attribute Controller and Video DAC Registers ........................................ 159 9.6 Color Registers.................................................................................... 163 9.7 Extended Registers.............................................................................. 165 9.8 VIDEO/TV Extended Registers ............................................................. 167 9.9 PCI Configuration Registers ................................................................. 172 9.10 AGP Configuration Registers ................................................................ 174 Register Summary / Description -- Legacy..................................................... 177 10.1 Register Summary ............................................................................... 177 10.1.1 Legacy ISA Registers................................................................... 177 Register Summary / Description - LPC Summary .......................................... 181 11.1 LPC Bridge Configuration Registers...................................................... 181 11.2 LPC Bridge Configuration Registers ...................................................... 182 Register Summary / Description -USB Summary........................................... 201 12.1 USB OpenHCI Host Controller Configuration Space............................... 201 12.1.1 USB Configuration Space............................................................. 201 12.2 USB OpenHCI Host Controller Operational Registers............................. 201 12.2.1 Host Controller Operational Registers ........................................... 202 12.3 Legacy Support Registers .................................................................... 226 Register Summary/Description-Fast Ethernet/Home Networking Summary ..... 231 ii Silicon Integrated Systems Corporation 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 13.1 MAC and PHY Registers ...................................................................... 231 13.1.1 MAC Configuration Space (Function 1) ......................................... 231 13.1.2 MAC Operational Registers .......................................................... 232 13.1.3 PHY Configuration Registers ........................................................ 232 10M/100M Ethernet Controller Registers ............................................... 233 PCI Configuration Registers ................................................................. 234 MAC Operational Registers .................................................................. 246 13.4.1 Wake-up Sample Frame Byte Mask Register................................. 272 MII PHY Registers ............................................................................... 272 Home SPI Registers............................................................................. 281 Register Summary / Description - Audio Accelerator Summary ...................... 289 Audio Configuration Space ( Function 4) ............................................... 289 14.1.1 Audio Configuration Registers:...................................................... 290 Operational Registers........................................................................... 298 14.2.1 Bit 7..0 X Timer1 Preset Value ..................................................... 307 14.2.2 Bit 0 1 Enable Timer 1................................................................. 308 14.2.3 Wave Engine Register:................................................................. 320 Register Summary / Description - SMBus ..................................................... 344 SMBUS Control Registers ................................................................... 344 Register Summary / Description - ACPI Summary......................................... 345 ACPI Configuration Registers ............................................................... 345 GPIOx Logic........................................................................................ 348 ACPI Register...................................................................................... 348 Register Ssummary / Description - Automatic Power Control Summary .......... 379 Automatic Power Control (APC) Registers ............................................. 379 17.1.1 RTC Registers............................................................................. 379 APC Register....................................................................................... 380 Electrical Characteristics .............................................................................. 387 Absolute maximum Ratings .................................................................. 387 DC Characteristics............................................................................... 387 18.2.1 DC Characteristics....................................................................... 387 18.2.2 DC Characteristics for DAC (Analog Output Characteristics)........... 388 Mechanical Dimension ................................................................................. 389 Power Sequence in SIS630 .......................................................................... 390 SIS630 Package on 4 Layer PCB ( With Heatsink) ................................ 391 SIS630 Package on 4 Layer PCB (Without Heatsink) ............................. 391 Copyright Notice .......................................................................................... 393
13.2 13.3 13.4 13.5 13.6 14 14.1 14.2
15 15.1 16 16.1 16.2 16.3 17 17.1 17.2 18 18.1 18.2
19 20 20.1 20.2 21
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Figure
Figure 1-1 SIS630 System Block Diagram .........................................................................2 Figure 1-2 SIS630: Ready for Easy PC .............................................................................3 Figure 6.2-1 PSON#.......................................................................................................56 Figure 6.2-2 ACPILED ...................................................................................................57 Figure 6.4-1 Arbiter Tree ................................................................................................62 Figure 6.5-1 The Mechanism of NAND Tree...................................................................63 Figure 6.5-2 The Test Scheme of NAND Tree ................................................................64 Figure 13.4-1 Receive Filter Algorithm........................................................................... 267 Figure 16.2-1 GPIOx Logic ........................................................................................... 348 Figure 20.2-1 SIS630 A Temp vs Power(2) .................................................................... 392
Table
TABLE 6.5-1 Nand Tree List for SIS630 Table 9.1-1 Sync Polarity vs. Vertical Screen Resolution................................................. 142 Table 9.1-2 Table for Video Clock Selection ................................................................... 142 Table 9.3-1 Table of Sequencer Registers...................................................................... 153 Table 9.4-2 Table of Function Select.............................................................................. 157 Table 9.4-3 Table of Rotate Count................................................................................. 157 Table 9.4-4 Table for Write Mode................................................................................... 158 Table 9.4-5 Table of Memory Address Select ................................................................. 158 Table 9.5-1 Table of Attribute Controller Registers.......................................................... 160 Table 9.5-2 Table for Video Read-back Through Diagnostic Bit (I) ................................... 162 Table 9.5-3 Table for Video Read-back Through Diagnostic Bit (II) .................................. 162 Table 9.5-4 Table of Pixel Panning ................................................................................ 162 Table 9.7-1 Table of Extended Registers........................................................................ 165 Table 9.8-2 Table of digital video interface registers........................................................ 171 Table11.1-1 Interrupt Pin Reroute Table......................................................................... 186 Table 18.1-1 Absolute Maximum Ratings....................................................................... 387 Table 18.2-1 DC Characteristics of Host, DRAM, PCI and IDE Interface ......................... 387 Table 18.2-1 Table of DC Characteristics for DAC .......................................................... 388
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Revision History
Date Rev Description 1.Revisions to Chapter 3 A4, A7,B4, C5, D5 ,M12,M13,M14 Pin List delete "EEDI/F8" 2.Revision to 3.4 Muxpin Ball No.W4 1.Removed GPIO9/PLED1#/OC4# in Chap.4. 2.Revisions to Chapter 4 USB (UV[4:0]) 3.Change "PLED0/OC3#/GPIO8" to "PLED0/OC2#/GPIO8" , "LDRQ1#/OC2#/GPIO2" to "LDRQ1#/OC3#/GPIO2" and "ACTIVITY indication" to "LINK/ACTIVITY indication" 4.Revision to 4.5 VGA Interface Name VBA1. 5.Revision to 4.12 PLED#. 6.Revision to 4.15 PHYVDD. 1.Add Arbiter Tree to Chap 6 2.Revisions to Mapping Table. 3.Revisions to 6.3 CPURST# and CKE. 1.Revision7.3.2 Register 08h. 1.Revisions to Chap.8 IDE Register 1.Revisions to 9.9 CNFG04,CNFG3C. 1. Revisions to Chap.10-11_South_Bridge Add an interrupt pin table. Change some description of Reg 40h Remove the description " These registers can be accessed from PCI bus and ISA bus". 1.Revisions to Chap.11 Register 5F Reg47, Reg48, Reg62 Reg72 , Reg73, Reg6a and Reg76 1.Revisions to Chap 14 (Audio)
Oct.1999
1.0
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1.Chap.16_Register Summary-ACPI.doc Register 4Ah and 4Bh must reverse. 2.In the summary table of registers, Register 4a and 4B would be changed. 3.Register 60~61h The description of bit0 has been changed for instantly power-off function. 4.Register 30~31h has changed for A1 version 1.Revisions to Chap.17 Reg02h,Reg03h,Reg02 bit6:5 ,Reg02 bit4:3, Reg02 bit2 ,Reg02 bit1, Reg03 bit7:6
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SIS630 Overview
The single chipset, SIS630, provides a high performance/low cost Desktop solution for the Intel Slot 1 and socket 370 series CPUs based system by integrating a high performance North Bridge, advanced hardware 2D/3D GUI engine and Super-South bridge. In addition, SIS630 provides system-on-chip solution that complies with Easy PC Initiative which supports Instantly Available/OnNow PC technology, USB, Legacy Removal and Slotless Design and FlexATX form factor. By integrating the UltraAGPTM technology and advanced 128-bit graphic display interface, SIS630 delivers AGP 4x performance and up to 2 GB/s memory bandwidth. Furthermore, SIS630 provides powerful hardware decoding DVD accelerator to improve the DVD playback performance. In addition to providing the standard interface for CRT monitors, SIS630 also provides the Digital Flat Panel Port (DFP) for a standard interface between a personal computer and a digital flat panel monitor. To extend functionality and flexibility, SiS also provides the " Video Bridge" (SiS301) to support the NTSC/PAL Video Output, Digital LCD Monitor and Secondary CRT Monitor, which reduces the external Panel Link transmitter and TV-Out encoder for cost effected solution. SIS630 also adopts Share System Memory Architecture which can flexibly utilize the frame buffer size up to 64MB. The " Super-South Bridge" in SIS630 integrates all peripheral controllers/accelerators /interfaces. SIS630 provides a total communication solution including 10/100Mb Fast Ethernet for Office requirement and 1Mb HomePNA for Home Networking. SIS630 offers AC' 97 compliant interface that comprises digital audio engine with 3D-hardware accelerator, on-chip sample rate converter, and professional wavetable along with separate modem DMA controller. SIS630 also provides interface to Low Pin Count (LPC) operating at 33 MHz clock which is the same as PCI clock on the host, and dual USB host controller with five USB ports that deliver better connectivity and 2 x 12Mb bandwidth. The built-in fast PCI IDE controller supports the ATA PIO/DMA, and the Ultra DMA33/66 function that supports the data transfer rate up to 66 MB/s. It provides the separate data path for two IDE channels that can eminently improve the performance under the multi-tasking environment. The following illustrates the system block diagram.
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
Slot1/ Socket370 CPU (100MHz FSB)
64bits/133MHZ 64bits/133MHZ
FBC 3 SDRAM DIMMs 5 USB Ports
LCD Monitor(Panel Link)
TV(NTSC,PAL)
SiS301 Video Bridge 100 TQFP (3 choose 1)
CRT(Secondary)
128-bit Graphics Engine (DVD H/W Acceleration)
RGB
Two IDE Ultra 66 SPDIF
SIS630
AC97 V2.1
AC97 Audio Codec AMR Modem Riser Card
Line In Line Out CD In PSTN
CRT(Primary)
PCI
Keyboard / PS2 Mouse PCI Device PCI Device PCI Device PCI Device 2 choose 1 10/100Mbps Ethernet RJ45 1M bps RJ11 Home Networking SiS900 Fast Ethernet MAC+PHY & Home PNA GPIOs SMBus
618 BGA
LPC
ISA BUS
Floppy drive
SiS950 LPC Super IO
(HW Monitoring)
Infra-Red
128 PQFP
LPC GPIOs LPC-to-ISA Flash COM 1 Bridge ROM COM 2 Parallel Port 7 Voltage, 3 Fan, Thermal Monitoring Game Port
Figure 1-1 SIS630 System Block Diagram
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
Slot1/ Socket370 CPU (100MHz FSB)
LCD Monitor(Panel Link)
TV(NTSC,PAL)
SiS301 Video Bridge 100 TQFP (3 choose 1)
64bits/133MHZ
CRT(Secondary) RGB CRT(Primary)
128-bit Graphics Engine (DVD H/W Acceleration)
FBC 3 SDRAM DIMMs 5 USB Ports Two IDE Ultra 66 SPDIF
64bits/133MHZ
SIS630
AC97 V2.1
AC97 Audio Codec AMR Modem Riser Card
Line In Line Out CD In PSTN
2 choose 1 10/100Mbps Ethernet RJ45 1M bps RJ11 Home Networking
SiS900 Fast Ethernet MAC+PHY & Home PNA
618 BGA
LPC Flash ROM
Figure 1-2 SiS 630: Ready for Easy PC
1.1
Bus # Bus 0 Bus 0 Bus 1 Bus 0 Bus 0
Function Block Reference Table
Device # Device 0 Device 0 Device 0 Device 1 Device 1 Function # Function 0 Function 1 Function 0 Function 0 Function 1 3 Device ID 0630h 5513h 6300h 0008h 0900h IDSEL AD11 AD11 AD11 AD12 AD12 Device Function North Bridge PCI IDE GUI LPC LAN
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bus 0 Bus 0 Bus 0 Bus 0 Bus 0 Device 1 Device 1 Device 1 Device 1 Device 2 Function 2 Function 3 Function 4 Function 6 Function 0 7001h 7001h 7018h 7013h 6001h AD12 AD12 AD12 AD12 AD13 USB 0 USB 1 H/W Audio S/W Modem Virtual PCI-to-PCI Bridge
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Features
Host Interface Controller n Supports Intel Pentium II/!!! CPU at 66MHz/100MHz Front Side Bus Frequency n Synchronous Host/DRAM Clock Scheme n Asynchronous Host/DRAM Clock Scheme Integrated DRAM Controller n 3-DIMM/6-Bank of 3.3V SDRAM n Supports NEC Virtual Channel Memory (VC-SDRAM) Technology n Supports Memory Bus up to 133 MHZ n System Memory Size up to 1.5 GB n Up to 512MB per Row n Supports 16Mb, 64Mb, 128Mb, 256Mb, 512Mb SDRAM Technology n Suspend-to-RAM (STR) n Relocatable System Management Memory Region n Programmable Buffer Strength for CS#, DQM[7:0], WE#, RAS#, CAS#, CKE, MA[14:0] and MD[63:0] n Shadow RAM Size from 640KB to 1MB in 16KB increments n Two Programmable PCI Hole Areas Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge n AGP v2.0 Compliant n Supports Graphic Window Size from 4MBytes to 256MBytes n Supports Pipelined Process in CPU-to-Integrated 3D A.G.P. VGA Access n Supports 8 Way, 16 Entries Page Table Cache for GART to Enhance Integrated A.G.P. VGA Controller Read/Write Performance n Supports PCI-to-PCI Bridge Function for Memory Write from 33Mhz PCI Bus to Integrated A.G.P. VGA Meet PC99 Requirements PCI 2.2 Specification Compliant High Performance PCI Arbiter n Supports up to 4 PCI Masters n Rotating Priority Arbitration Scheme n Advanced Arbitration Scheme Minimizing Arbitration Overhead. n Guaranteed Minimum Access Time for CPU And PCI Masters Integrated Host-To-PCI Bridge n Zero Wait State Burst Cycles n CPU-to-PCI Pipeline Access n 256B to 4KB PCI Burst Length for PCI Masters n PCI Master Initiated Graphical Texture Write Cycles Re-mapping Preliminary V.10 Oct.07,1999 5 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset n Reassembles PCI Burst Data Size into Optimized Block Size Fast PCI IDE Master/Slave Controller n Supports PCI Bus Mastering n Native Mode and Compatibility Mode n PIO Mode 0, 1, 2 , 3, 4 n Multiword DMA Mode 0, 1, 2 n Ultra DMA 33/66 n Two Independent IDE Channels Each with 16 DW FIFO Virtual PCI-to-PCI Bridge Integrated Ultra AGP VGA for Hardware 2D/3D Video/Graphics Accelerators n Supports Tightly Coupled 64 Bits 100mhz Host Interface to VGA to Speed Up GUI Performance and Video Playback Frame Rate n AGP v. 2.0 Compliant n Zero-Wait-State 128x4 Post-Write Buffer with Write Combine Capability n Zero-Wait-State 128x4 2-Way Read Ahead Cache Capability n Re-locatable Memory-Mapped and I/O Address Decoding n Flexible Design Shared Frame Buffer Architecture for Display Memory n Shared System Memory Area up to 64MB n Built-in 8K Bytes Texture Cache n 32-Bit VLIW Floating-Point Primitive Setup Engine n Peak Polygon Rate: 4M Polygon/Sec @ 1 Pixel/Polygon With 16bpp, Bilinear Textured, Z Buffered And Alpha Blended n Supports Flat and Gouraud Shading n Supports High Quality Dithering n Supports Z-Test, Stencil Test, Alpha Test and Scissors Clipping Test n Supports Z Pre-Test for Reducing Texture Read DRAM Bandwidth n Supports 256 Rops n Supports Individual Z-Buffer and Render Buffer at the Same Time n Supports 16/24/32 BPP Z Buffer Integer/Floating Formats n Supports 16/32 BPP Render Buffer Format n Supports 1/2/4/8 Stencil Format n Supports Per-Pixel Texture/Fog Perspective Correction n Supports MIPMAP with Point-Sampled, Linear, Bi-Linear and Tri-Linear Texture Filtering n Supports Single Pass Two MIPMAP Texture, One Texture on Clock n Supports up to 2048x2048 Texture Size n Supports 2' S Power of Width and Height Structure Rectangular Texture n Supports 1/2/4/8 BPP Palletize Texture with 32 Bit ARGB Format n Supports Palette for High Performance Palette Look Up Preliminary V.10 Oct.07,1999 6 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n Supports 1/2/4/8 BPP Luminance Texture Supports 1/2/4/8 BPP Intensity Texture Supports 8/16/24/32 BPP RGB/ARGB Texture Format Supports Video YUV Texture in All Supported Texture Formats Supports MIP-Mapped Texture Transparency, Blending, Wrapping, Mirror and Clamping Supports Fogging and Alpha Blending Supports Vertex Fogging, Linear Fogging Table and Non-Linear Fogging Table Supports Specula Lighting Supports Sort Dependent Edge Anti-Aliasing Supports Full Scene Anti-Aliasing Supports Hardware Back Face Culling Internal Full 32 Bits ARGB Format Ultra Pipelined Architecture for Ultra High Performance and High Rendering Quality 128-Bit 2D Engine with a Full Instruction Set Built-In 64x64x2 Bit-Mapped Hardware Cursor Built-In 32x32x16, 32x32x32 Bit-Mapped Color Hardware Cursor Maximum 64 MB Frame Buffer with Linear Addressing MPEG-2 ISO/IEC 13818-2 MP@ML and MPEG-1 ISO/IEC 11172-2 Standards Compliant Supports Hardware DVD Accelerator Direct DVD to TV Playback Supports Single Frame Buffer Architecture Supports Two Independent Video Windows with Overlay Function and Scaling Factors Supports YUV-To-RGB Color Space Conversion Supports Bi-Linear Video Interpolation with Integer Increments of Pixel Accuracy Supports Graphic and Video Overlay Function Supports CD/DVD to TV Playback Mode Simultaneous Graphic and TV Video Playback Overlay Supports Current Scan Line of Refresh Red-Back and Interrupt Supports Tearing Free Double/Triple Buffer Flipping Supports Input Video Vertical Blank or Line Interrupt Supports RGB555, RGB565, YUV422 and YUV420 Video Playback Format Supports Filtered Horizontal Up and Down Scaling Playback Supports DVD Sub-Picture Playback Overlay Supports DVD Playback Auto-Flipping Built-in Two Video Playback Line Buffers Supports DCI Drivers Supports Direct Draw Drivers 7 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset n n n n n n n n n n Built-in Programmable 24-bit True-Color RAMDAC up to 270 MHz Pixel Clock RAMDAC Snoop Function Built-in Reference Voltage Generator and Monitor Sense Circuit Supports Down-Loadable RAMDAC for Gamma Correction in High Color and True Color Modes Built-in Dual-Clock Generator Supports Multiple Adapters and Multiple Monitors Built-in PCI Multimedia Interface Supports Digital Flat Panel Port for Digital Monitor (LCD Panel) Built-in VESA Plug and Display for CH7003, PanelLinkTM and LVDS Digital Interface Built-in Secondary CRT Controller for Independent Secondary CRT, LCD or TV digital output Supports VESA Standard Super High Resolution Graphic Modes - 640x480 - 800x600 - 1024x768 16/256/32K/64K/16M colors 120 Hz NI 16/256/32K/64K/16M colors 120 Hz NI 256/32K/64K/16M colors 120 Hz NI
- 1280x1024 256/32K/64K/16M colors 120 Hz NI - 1600x1200 256/32K/64K/16M colors 100 Hz NI - 1920x1200 256/32K/64K/16M colors 80 Hz NI n Low Resolution Modes n Supports Virtual Screen up to 4096x4096 n Fully Directx 6.0 Compliant n Efficient and Flexible Power Management with ACPI Compliance n Supports DDC1, DDC2B and DDC 3.0 Specifications n Cooperate with " SiS Video Bridge" to Support - NTSC/PAL Video Output - Digital LCD Monitor - Secondary CRT Monitor Low Pin Count Interface n Forwards PCI I/O and Memory Cycles into LPC Bus n Translates 8-/16-bit DMA Cycles into PCI Bus Cycles Advanced PCI H/W Audio & Modem n Advanced Wavetable Synthesizer - 64-Voices Polyphony Wavetable Synthesizer Supports All Combinations of Stereo/Mono, 8-/16-bits, and Signed/Unsigned Samples - Per Channel Volume and Envelop Control, Pitch Shift, Left/Right Pan, Tremolo, and Vibrato - Global Effect Process for Reverb, Chorus and Echo Preliminary V.10 Oct.07,1999 8 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset - DirectMusicTM Support with Unlimited Downloadable Samples in System Memory - DLS-1-Compatible Downloadable Samples Support n DirectSoundTM 3D - 64-Voice DirectSoundTM Channels - 32-Voice DirectSoundTM 3D Accelerator with IID, IAD and Doppler Effects on 3D Positional Audio buffer - DirectSound Accelerator for Volume, Pan and Pitch Shift Control on Streaming or Static Buffers - VirtualHRTF Interactive 3D Positional Audio Accelerator for DirectXTM 5/6 n Advanced Streaming Architecture - Microsoft WDM Streaming Architecture Compliant and Re-routable Endpoint Support - Three Stereo Capture Channels - AC' 97/98 Stereo Recording Channel Through AC-Link n High Quality Audio and AC' 97/98 Support - CD Quality Audio with 90dB+ SNR Using External High Quality AC' 97/98 CODEC - AC' 97/98 Support with Full Duplex, Independent Sample Rate Converter for Audio Recording and Playback - On-Chip Sample Rate Converter Ensures All Internal Operation at 48KHz - High Precision Internal 26-bit Digital Mixer with 20-bit Digital Audio Output n Full Legacy Compatibility - SoundBlaster Pro/16 - VirtualFMTM Enhances Audio Experience through Realtime FM-to-Wavetable Conversion - MPU-401 Compatible UART for External or Internal Synthesis n Telephony & Modem - Full Duplex VirtualPhone Speaker Phone with Modem Capable AC' 97/98 - HSP V.90 Modem n Software Support - Complete DirectX Driver Suite(DirectSound3D, DirectSound, DirectMusic, DirectInput) for Windows 98/Windows 2000 - Configuration Installation and Diagnostics under Real Mode DOS, Windows 98 DOS Box - Windows 98/NT5.0 Configuration, Installation and Mixer Program n Extras - 2-to-6 Speakers Output with Optional VirtaulFX ,VirtualAC3 - DirectX Timer for Video/Audio Synchronization Preliminary V.10 Oct.07,1999 9 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset - I2S and SPDIF Interface Advanced Power Management n Meets ACPI 1.0 Requirements n Meets APM 1.2 Requirements n ACPI Sleep States Include S1, S2, S3, S4, S5 n CPU Power States Include C0, C1, C2 C3 n Power Button with Override n RTC Day-of-Month, Month-of-Year Alarm n 24-bit Power Management Timer n LED Blinking in S0,S1,S2 and S3 States n System Power-Up Events Include: Power Button, Hot-Key, Keyboard Password/ HotKey, RTC Alarm, Modem Ring-In, SMBALY#, LAN, PME#, AC' 97 Wake-Up and USB Wake-Up n Software Watchdog Timer n Power Supply' 98 Support n PCI Bus Power Management Interface Spec. 1.0 Integrated DMA Controller n Two 8237A Compatible DMA Controllers n 8/16- bit DMA Data Transfer n Distributed DMA Support Integrated Interrupt Controller n Two 8237A Compatible DMA Controllers n Two 8259A Compatible Interrupt Controllers n Level- or Edge-Triggered Programmable n Serial IRQ n Interrupt Sources Re-routable to Any IRQ Channel Three 8254 Compatible Programmable 16-bit Counters n System Timer Interrupt n Generate Refresh Request n Speaker Tone Output Integrated Keyboard Controller n Hardwired Logic Provides Instant Response n Supports PS/2 Mouse Interface n Password Security and Password Power-Up n System Sleep and Power-Up by Hot-Key n KBC and PS2 Mouse Can Be Individually Disabled Integrated Real Time Clock(RTC) with 256B CMOS SRAM Preliminary V.10 Oct.07,1999 10 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset n Supports ACPI Day-of-Month and Month-of-Year Alarm n 256 Bytes of CMOS SRAM n Provides RTC H/W Year 2000 Solution Universal Serial Bus Host Controller n OpenHCI Host Controller with Root Hub n Two USB Host Controller n Five USB Ports n Supports Legacy Devices n Over Current Detection I2C Bus/SMBUS Series Interface Integrated Fast Ethernet Controller and 10/100 Megabit Per Second (Mbps) Physical Layer Transceivers for the PCI Local Bus n Plug and Play Compatible n High-Performance 32-Bit PCI Bus Master Architecture with Integrated Direct Memory n Access (DMA ) Controller for Low CPU and Bus Utilization n Supports an Unlimited PCI Burst Length n Supports Big Endian and Little Endian Byte Alignments n Supports PCI Device ID, Vendor ID/Subsystem ID, Subsystem Vendor ID Programming through the EEPROM Interface n Implements Optional PCI 3.3v Auxiliary Power Source 3.3Vaux Pin And Optional PCI n IEEE 802.3 and 802.3u Standard Compatible n IEEE 802.3u Auto Negotiation and Parallel Detection for Automatic Speed Selection n Full Duplex and Half Duplex Mode for Both 10 and 100 Mbps n Fully Compliant Ansi X3.263 Tp-Pmd Physical Sub-Layer Which Includes Adaptive Equalization and Baseline Wander Correction. n Automatic Jam and IEEE 802.3x Auto-Negotiation for Flow Control n Single Access to Complete PHY Register Set n Built-In Waveform Shaping Requires No External Filters n Single 25MHz Clock for 10 and 100 Mbps Operation n Power Down of 10base-T/100base-Tx Sections When not in Use n Jabber Control and Auto-Polarity Correction for 10base-T n User Programmable LED Function Mapping n Supports Software, Enhanced Software, and Automatic Polling Schemes to Internal PHY Status Monitor and Interrupt n Supports 10base-T, 100base-Tx NAND Tree for Ball Connectivity Testing 618-Balls BGA Package 1.8V Core with Mixed 3.3V and 5V I/O CMOS Technology Preliminary V.10 Oct.07,1999 11 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
3
3.1
3.1.1
Pin Assignment
Pin Assignment (Top View)
SIS630 Pin Assignment (Top View-Left Side)
1 A B C D PMDAT PSON#
2
3 AC_SDIN0
4 TXAVDD RXAVDD
AC_RESET#
5 REXT OSC25MHI RXAVSS PLED0#
6 HRTXRXN HRTXRXP EESK EECS
7 GPIO2 GPIO6 GPIO5 GPIO4
8 AC_SYNC
AC_BIT_CLK
9
AD2
10 C/BE0# AD7 AD6 AD4
11 AD13 AD11 AD10 AD9
12 STOP# PAR AD15 AD14
13 FRAME# TRDY# DEVSEL# PLOCK#
14 AD19 AD18 AD16 C/BE2#
15 AD20 AD22 AD23 C/BE3#
SMBALT# PMCLK ACPILED
AC_SDIN1 KLOCK# KBDAT
AD1 AD0 AC_SDOUT
GPIO7
THERM# GPIO0
KBCLK
E F G H J K
USBVDD UV3+ RTCVDD
OSC32KHO
UV3USBVDD AUXOK OSC32KHI SMCLK LAD3
PWRBTN# UV2+ UV0+ PWROK INTD# SPK
RING UV4UV1+ RTCVSS INTC# SMBDAT
PME# UV4+ UV2UV0INTB# INTA#
PCIRST# CKE
EEDO
GPIO1 EEDI
AD3 EXTSMI#
AD5
AD12 AD8
C/BE1#
AD17 IRDY#
AD21 AD24
UV1TPIBATOK
OVDD(AUX)
VCC3 TPI+ TPOTPO+ VCC3 VCC3
VCC3 VCC3
CLK48M LAD1
L M N P R T
VMD63 VMD58 VDQM6 VMD53 VMD49 VMD47
SIRQ VMD60 VDQM7 VMD55 VMD50 VMD46
LFRAME# VMD61 VMD56 VDQM4 VMD51 VMD45
LAD2 VMD62 VMD57 VDQM5 VMD52 VMD43
SERR# LDRQ# VMD59 VMD54 VMD44 VMD40 VCS# VMD48 VMD32 LAD0 VCC3 VCC3 VCC3 VCC3
IVDD(AUX)
VCC3 VCC3 VCC3 VCC3 VCC3
RXAVSS VSS VSS VSS VSS
TXAVSS VSS VSS VSS VSS
OSC25AVSS
VSS VSS VSS VSS VSS
VSS VSS VSS VSS
U V W Y AA AB
VMD42 VMD37 VMD33 VMD30 VMD24 VMD22
VMD41 VMD36 VMA10 VMD29 VDQM2 VMD21
VMD39 VMD35 VMA11 VMD28 VDQM1 VMD20
VMD38 VMD34 VBA1 VMD26 VDQM0 VMD19
VMD31 VMD27 VMD23 VMD25 VMD7 VMD18 SSYNC VMD15 VDQM3
VCC3 VCC3 IVDD IVDD IVDD IVDD IVDD
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VCC3
VCC3
VCC3 VCC3
VCC3 VCC3
AC AD AE AF AG
VMD17 VMD11 VMD5 VMD1 OSCI
VMD16 VMD10 VMD4 VMD0 HSYNC
VMD14 VMD9 VMD3 VSYNC DDCDATA
DCLKAVDD
VMD13 VMD8 VMD2 COMP RSET
VMD12 VMD6 IDA7 IDA6 IDA9 IDA5 IDA4 IDA11 IDA3 IDA8 IDA10 IDA1
Ver 0.73 5.13.1999
IDA12 IIOWA# ICHRDYA IIORA# IDA13 IDSAA0 IDSAA2 IDA14
IDB7
IIRQA IDREQA IDB11 IDB3 CBLIDA IDB1 IDB0 IDB8 IIORB# ICHRDYB
IDB10 IDB12 IDSAB0 IDECSB0#
IDB14 IDREQB
IIRQB
IDB6
IDB9
ENTEST
AH AJ 1
DDCCLK
VREF BOUT 4
ROUT GOUT 5
DACAVDD IDA2 6
IDA0 IDA15 7
IDACKA# IDSAA1 8
IDECSA0# IDECSA1# 9
IDB5 IDB4 10
IDB2 IDB13 11
IDB15 IIOWB# 12
IDACKB# IDSAB1 13
IDECSB1# PCICLK 14
IDEAVDD
SDCLK
ECLKAVDD
2
3
15
Preliminary V.10 Oct.07,1999
12
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3.1.2 SIS630 Pin Assignment (Top View-Right Side)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
AD25
AD30
CPUCLK
CPUAVDD
FERR#
HD61#
HD53#
VTTB
GTLREFB
HD36#
HD38#
HD28#
A
AD26
AD31
PREQ2#
INIT#
IGNE#
HD55#
HD57#
HD49#
VSSQ
HD40#
HD33#
HD31#
HD30#
B
AD27
PGNT1#
PREQ0#
STPCLK#
INTR
HD56#
HD59#
HD51#
HD47#
HD43#
HD32#
HD29#
HD26#
HD27#
C
AD29
PGNT0#
SMI#
CPUSLP#
HD62#
HD50#
HD46#
HD41#
HD45#
HD34#
HD35#
HD25#
HD24#
HD22#
D
AD28
PREQ1#
A20M#
HD63#
HD58#
HD54#
HD48#
HD42#
HD44#
HD37#
HD23#
HD19#
HD21#
HD18#
E
PGNT2#
NMI
HD60#
HD52#
HD39#
HD16#
HD13#
HD17#
HD11#
HD15#
F
HD10#
HD14#
HD7#
HD9#
HD6#
G
VCC3
HD20#
HD8#
HD5#
HD2#
HD0#
HD1#
H
VCC3
VCC3
VCC3
IVDD
IVDD
IVDD
HD12#
BREQ0#
HA29#
HA30#
HA26#
J
IVDD
HD4#
HA31#
HA27#
HA28#
HA20#
HA23#
K
IVDD
HD3#
HA25#
HA19#
HA15#
HA18#
L
VSS VSS
VSS VSS
VSS VSS
VCC3 VCC3
CPURST#
HA24# HA22#
HA17# HA8#
HA11# HA7#
HA13# HA5#
HA12# VTTA
M N
VSS
VSS
VSS
VCC3
VCC3
HA21#
HA16#
HA9#
HA6#
HA4#
GTLREFA
P
VSS
VSS
VSS
VCC3
VCC3
HA10#
HA14#
BPRI#
HREQ0#
BNR#
VSSQ
R
VSS
VSS
VSS
VCC3
VCC3
HTRDY#
HA3#
HLOCK#
DEFER#
HREQ4#
HREQ1#
T
VSS
VSS
VSS
VCC3
HREQ3#
HITM#
RS0#
DRDY#
HREQ2#
U
VSS
VSS
VSS
VCC3
MD62
HIT#
RS1#
RS2#
ADS#
DBSY#
V
IVDD
MD58
MD29
MD30
MD63
MD31
W
IVDD
MD56
MD59
MD27
MD60
MD28
MD61
Y
VCC3
VCC3
VCC3
IVDD
IVDD
IVDD
MD54
MD24
MD57
MD25
MD26
AA
VCC3
MD48
MD53
MD21
MD22
MD55
MD23
AB
CSB3#
MD51
MD19
MD52
MD20
AC
CBLIDB
MD40
MD46
CSA4#
DQM3
MD16
MD49
MD17
MD50
MD18
AD
IDSAB2
MD34
MD38
MD42
MD11
SCAS#
DQM4
CSA5#
MA0
CSB1#
CSB0#
DQM6
DQM2
DQM7
AE
MD33
MD3
MD5
MD8
MD43
MD13
WE#
SRAS#
CSA0#
MA4
MA14
CSB5#
CSB4#
CSB2#
AF
MD0
MD35
MD37
MD7
MD10
MD45
MD15
DQM1
CSA1#
MA3
MA7
MA11
MA12
MA13
AG
MD32
MD2
MD4
MD39
MD9
MD12
MD47
DQM5
CSA2#
MA2
MA6
MA9
MA10
AH
SDAVDD
MD1
MD36
MD6
MD41
MD44
MD14
DQM0
CSA3#
MA1
MA5
MA8
AJ
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Preliminary V.10 Oct.07,1999
13
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
3.2
SIS630 Alphabetical Pin List
SIGNAL NAME SIS630 BALL No. SIGNAL NAME SIS630 BALL No. SIGNAL NAME SIS630 BALL No.
A20M# AC_BIT_CLK AC_RESET# AC_SDIN0 AC_SDIN1 AC_SDOUT AC_SYNC ACPILED AD0 AD1 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD2 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29
E18 B8 C4 A3 B3 D9 A8 D2 C9 B9 C11 B11 E12 A11 D12 C12 C14 E14 B14 A14 A9 A15 E15 B15 C15 F15 A16 B16 C16 E16 D16
AD3 AD30 AD31 AD4 AD5 AD6 AD7 AD8 AD8 AD9 ADS# AUXOK BATOK BNR# BOUT BPRI# BREQ0# C/BE0# C/BE0# C/BE1# C/BE2# C/BE3# CBLIDA CBLIDB CKE CLK48M COMP CPUAVDD 14
E10 A17 B17 D10 E11 C10 B10 F12 F12 D11 V28 G2 K6 R28 AJ4 R26 J26 A10 A10 E13 D14 D15 AE12 AD16 F6 J1 AF4 A19
CPUCLK CPURST# CPUSLP# CSA0# CSA1# CSA2# CSA3# CSA4# CSA5# CSB0# CSB1# CSB2# CSB3# CSB4# CSB5# DACAVDD DBSY# DCLKAVDD DDCCLK DDCDATA DEFER# DEVSEL# DQM0 DQM1 DQM2 DQM3 DQM4 DQM5
A18 M24 D19 AF24 AG24 AH24 AJ24 AD22 AE23 AE26 AE25 AF29 AC25 AF28 AF27 AH6 V29 AH3 AH2 AG3 T27 C13 AJ23 AG23 AE28 AD24 AE22 AH23
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
SIGNAL NAME SIS630 BALL No. SIGNAL NAME SIS630 BALL No. SIGNAL NAME SIS630 BALL No.
DQM6 DQM7 DRDY# ECLKAVDD EECS EEDI EEDO EESK EESK ENTEST EXTSMI# FERR# FRAME# GOUT GPIO0 GPIO1 GPIO2 GPIO4 GPIO5 GPIO6 GPIO7 GTLREFA GTLREFB HA10# HA11# HA12# HA13# HA14# HA15#
AE27 AE29 U28 AJ3 D6 F8 E7 C6 C6 AG15 F10 A20 A13 AJ5 D8 E8 A7 D7 C7 B7 E9 P29 A24 R24 M27 M29 M28 R25 L28
HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA3# HA30# HA31# HA4# HA5# HA6# HA7# HA8# HA9# HD0# HD1# HD10# HD11# HD12# HD13# HD14# 15
P25 M26 L29 L27 K28 P24 N25 K29 M25 L26 J29 K26 K27 J27 T25 J28 K25 P28 N28 P27 N27 N26 P26 H28 H29 G25 F28 J25 F26 G26
HD15# HD16# HD17# HD18# HD19# HD2# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD3# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD4# HD40# HD41#
F29 F25 F27 E29 E27 H27 H24 E28 D29 E26 D28 D27 C28 C29 A27 C27 L25 B28 B27 C26 B26 D25 D26 A25 E25 A26 F24 K24 B25 D23
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
SIGNAL NAME SIS630 BALL No. SIGNAL NAME SIS630 BALL No. SIGNAL NAME SIS630 BALL No.
HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD5# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD6# HD60# HD61# HD62# HD63# HD7# HD8# HD9# HIT# HITM# HLOCK#
E23 C25 E24 D24 D22 C24 E22 B23 H26 D21 C23 F22 A22 E21 B21 C21 B22 E20 C22 G29 F20 A21 D20 E19 G27 H25 G28 V25 U26 T26
HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HRTXRXN HRTXRXP HSYNC HTRDY# ICHRDYA ICHRDYB IDA0 IDA1 IDA10 IDA11 IDA12 IDA13 IDA14 IDA15 IDA2 IDA3 IDA4 IDA5 IDA6 IDA7 IDA8 IDA9 IDACKA# IDACKB# IDB0 16
R27 T29 U29 U25 T28 A6 B6 AG2 T24 AF8 AG13 AH7 AG7 AF7 AF6 AD8 AE9 AD10 AJ7 AJ6 AG6 AE6 AD6 AF5 AE5 AE7 AG5 AH8 AH13 AG12
IDB1 IDB10 IDB11 IDB12 IDB13 IDB14 IDB15 IDB2 IDB3 IDB4 IDB5 IDB6 IDB7 IDB8 IDB9 IDEAVDD IDECSA0# IDECSA1# IDECSB0# IDECSB1# IDREQA IDREQB IDSAA0 IDSAA1 IDSAA2 IDSAB0 IDSAB1 IDSAB2 IGNE# IIORA#
AF12 AD14 AF11 AE14 AJ11 AD15 AH12 AH11 AG11 AJ10 AH10 AF10 AE10 AE13 AG10 AH15 AH9 AJ9 AG14 AH14 AE11 AE15 AF9 AJ8 AG9 AF14 AJ13 AE16 B20 AG8
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
SIGNAL NAME SIS630 BALL No. SIGNAL NAME SIS630 BALL No. SIGNAL NAME SIS630 BALL No.
IIORB# IIOWA# IIOWB# IIRQA IIRQB INIT# INTA# INTB# INTC# INTD# INTR IRDY# KBCLK KBDAT KLOCK# LAD0 LAD1 LAD2 LAD3 LDRQ# LFRAME# MA0 MA1 MA10 MA11 MA12 MA13 MA14 MA2 MA3
AF13 AE8 AJ12 AD12 AF15 B19 K5 J5 J4 J3 C20 F14 D4 D3 C3 M6 K1 L4 K2 M5 L3 AE24 AJ25 AH28 AG27 AG28 AG29 AF26 AH25 AG25
MA4 MA5 MA6 MA7 MA8 MA9 MD0 MD1 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD2 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD3 17
AF25 AJ26 AH26 AG26 AJ27 AH27 AG16 AJ17 AG20 AE20 AH21 AF21 AJ22 AG22 AD25 AD27 AD29 AC27 AH17 AC29 AB26 AB27 AB29 AA26 AA28 AA29 Y26 Y28 W26 AF17
MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD4 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD5 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57
W27 W29 AH16 AF16 AE17 AG17 AJ18 AG18 AE18 AH19 AH18 AD18 AJ20 AE19 AF20 AJ21 AG21 AD20 AH22 AB24 AD26 AF18 AD28 AC26 AC28 AB25 AA25 AB28 Y24 AA27
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
SIGNAL NAME SIS630 BALL No. SIGNAL NAME SIS630 BALL No. SIGNAL NAME SIS630 BALL No.
MD58 MD59 MD6 MD60 MD61 MD62 MD63 MD7 MD8 MD9 NMI
OSC25AVSS
W25 Y25 AJ19 Y27 Y29 V24 W28 AG19 AF19 AH20 F18 M14 B5 H2 H1 AG1 B12 AJ14 E6 D17 C17 F16 D5 D13 C2 C1 E5 C18 E17 B18
PSON# PWRBTN# PWROK REXT RING ROUT RS0# RS1# RS2# RSET RTCVDD RTCVSS RXAVDD RXAVSS RXAVSS SCAS# SDAVDD SDCLK SERR# SIRQ SMBALT# SMBDAT SMCLK SMI# SPK SRAS# SSYNC STOP# STPCLK# 18
D1 E3 H3 A5 E4 AH5 U27 V26 V27 AG4 G1 H4 B4 M12 C5 AE21 AJ16 AJ15 L5 L2 B2 K4 J2 D18 K3 AF23 AB6 A12 C19
THERM# TPITPI+ TPOTPO+ TRDY# TXAVDD TXAVSS USBVDD USBVDD UV0UV0+ UV1UV1+ UV2UV2+ UV3UV3+ UV4UV4+ VBA1 VCS# VDQM0 VDQM1 VDQM2 VDQM3 VDQM4 VDQM5 VDQM6 VDQM7 VMA10
C8 J9 J10 J11 J12 B13 A4 M13 E1 F2 H5 G3 H6 G4 G5 F3 E2 F1 F4 F5 W4 P6 AA4 AA3 AA2 V6 P3 P4 N1 N2 W2
OSC25MHI OSC32KHI OSC32KHO OSCI PAR PCICLK PCIRST# PGNT0# PGNT1# PGNT2# PLED0# PLOCK# PMCLK PMDAT PME# PREQ0# PREQ1# PREQ2#
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
SIGNAL NAME SIS630 BALL No. SIGNAL NAME SIS630 BALL No. SIGNAL NAME SIS630 BALL No.
VMA11 VMD0 VMD1 VMD10 VMD11 VMD12 VMD13 VMD14 VMD15 VMD16 VMD17 VMD18 VMD19 VMD2 VMD20 VMD21 VMD22 VMD23 VMD24 VMD25 VMD26 VMD27 VMD28 VMD29 VMD3 VMD30 VMD31 VMD32 VMD33 VMD34 VMD35
W3 AF2 AF1 AD2 AD1 AC5 AC4 AC3 Y6 AC2 AC1 AB5 AB4 AE4 AB3 AB2 AB1 W5 AA1 Y5 Y4 V5 Y3 Y2 AE3 Y1 U5 T6 W1 V4 V3
VMD36 VMD37 VMD38 VMD39 VMD4 VMD40 VMD41 VMD42 VMD43 VMD44 VMD45 VMD46 VMD47 VMD48 VMD49 VMD5 VMD50 VMD51 VMD52 VMD53 VMD54 VMD55 VMD56 VMD57 VMD58 VMD59 VMD6 VMD60 VMD61 VMD62 19
V2 V1 U4 U3 AE2 T5 U2 U1 T4 R5 T3 T2 T1 R6 R1 AE1 R2 R3 R4 P1 P5 P2 N3 N4 M1 N5 AD5 M2 M3 M4
VMD63 VMD7 VMD8 VMD9 VREF VSSQ VSSQ VSYNC VTTA VTTB WE#
L1 AA5 AD4 AD3 AH4 R29 B24 AF3 N29 A23 AF22
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
3.3
Power Plane
* 630 POWER
HOS DRAM
Preliminary V.10 Oct.07,1999
HOST DRAM
CCLK 3.3V
NORTH + SOUTH + GUI IVDD 1.8V
MCLK 3.3 V
PCLK 1.8 V
PCI
HOMEPHYAFE 3.3V
IDE IDE
OVDD 3.3V PVDD 3.3V
AUX
AUX
IVDD_AUX 1.8V
RTC 1.8 V RTC
PHY_ANALOG025 3.3V
SOUTH
1.8V
DAC 3.3V
GUI
DCLK 3.3V
ECLK 3.3V
SOUTH
VMD,VDQM,VCS,VMA
GUI
OVDD_AUX 3.3V PVDD_AUX 3 .3V
RTC 1.8V
20
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
3.4
Muxpin
Name EEDO GPIO0 GPIO1 GPIO2 GPIO7 KBCLK KBDAT PLED0 PMCLK PMDAT KLOCK SMBALT# VBA1 VMA10 VMA11 VMD28 VMD29 VMD30 VMD31 VMD32 VMD33 VMD34 VMD35 VMD36 VMD37 VMD38 VMD39 MUX GPIO3 PREQ3#/OC0# PGNT3#/OC1# LDRQ1#/OC3# SPDIF GPIO11 GPIO10 GPIO8/OC2# GPIO13 GPIO12 GPIO14 GPIO15
VBCLK/PLPWDN#
Ball No E7 D8 E8 A7 E9 D4 D3 D5 C2 C1 C3 E4 W4 W2 W3 Y3 Y2 Y1 U5 T6 W1 V4 V3 V2 V1 U4 U3
Default Function GPIO3 GPIO0 GPIO1 GPIO2 GPIO7 GPIO11 GPIO10 GPIO8 GPIO13 GPIO12 GPIO14 GPIO15 VBCLK VMA10 VMA11 VMD28 VMD29 VMD30 VMD31 VMD32 VMD33 VMD34 VMD35 VMD36 VMD37 VMD38 VMD39 21
Controlled by APC_R02B0 APC_R03B6 APC_R03B6 APC_R03B7 APC_R02B2 APC_R02B[6:5] APC_R02B[6:5] APC_R02B[4:3] APC_R02B[6:5] APC_R02B[6:5] APC_R02B[6:5] APC_R02B7 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33
MA10/VBHCLK MA11/VGCLK DDC2DATA DDC2CLK VBVSYNC VBHSYNC VBCAD TVCTL1 TVCTL0 VBBLANKN VBRGB15 VBRGB14 VBRGB12 VBRGB13
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset T5 U2 U1 T4 R5 T3 T2 T1 R6 R1 R2 R3 R4 P1 P5 P2 N3 N4 M1 N5 VMD40 VMD41 VMD42 VMD43 VMD44 VMD45 VMD46 VMD47 VMD48 VMD49 VMD50 VMD51 VMD52 VMD53 VMD54 VMD55 VMD56 VMD57 VMD58 VMD59 VBRGB8 VBRGB9 VBRGB11 VBRGB10 VBRGB23 VBRGB22 VBRGB21 VBRGB20 VBRGB19 VBRGB16 VBRGB17 VBRGB18 VBRGB0 VBRGB1 VBRGB2 VBRGB3 VBRGB4 VBRGB5 VBRGB6 VBRGB7 VMD40 VMD41 VMD42 VMD43 VMD44 VMD45 VMD46 VMD47 VMD48 VMD49 VMD50 VMD51 VMD52 VMD53 VMD54 VMD55 VMD56 VMD57 VMD58 VMD59 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33 H/W MD36&MD33
Preliminary V.10 Oct.07,1999
22
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
4
Pin Description (Preliminary)
Power Plane: Aux: Power exists regardless the system is power down or power up unless the power cord is disconnected. Main: Power exists only the system is power up. RTC: Battery power.
4.1
Host Bus Interface
Name CPUCLK ADS# Tolerance 3.3V/5V 1.5V Power Plane MAIN MAIN Type Attr I I/O GTL+ Description Host Clock : Address Strobe : Address Strobe is driven by CPU to indicate the start of a CPU bus cycle. Request Command: HREQ[4:0]# are used to define each transaction type during the clock when ADS# is asserted and the clock after ADS# is asserted. Symmetric Agent Bus Request: BREQ0# is driven by the symmetric agent to request for the bus. Block Next Request: This signal can be driven asserted by any bus agent to block further requests being pipelined. Host Lock : CPU asserts HLOCK# to indicate the current bus cycle is locked. Keeping a Non-Modified Cache Line:
HREQ[4:0]#
1.5V
MAIN
I/O GTL+
BREQ0#
1.5V
MAIN
O GTL+ I/O GTL+
BNR#
1.5V
MAIN
HLOCK#
1.5V
MAIN
I GTL+ I/O GTL+
HIT#
1.5V
MAIN
Preliminary V.10 Oct.07,1999
23
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset HITM# 1.5V MAIN I/O GTL+ Hits a Modified Cache Line: Hit Modified indicates the snoop cycle hits a modified line in the L1 cache of CPU. Defer Transaction Completion: SIS630 will use this signal to indicate a retry response to host bus. Response Status: RS[2:0]# are driven by the response agent to indicate the transaction response type. The following shows the response type. RS[2:0] Response 000 Idle State 100 Reserved 001 Retry 101 No data 010 Reserved 110 Implicit Write-back 011 Reserved 111 Normal Data Target Ready: During write cycles, response agent will drive TRDY# to indicate the agent is ready to accept data. Data Ready: DRDY# is driven by the bus owner whenever the data is valid on the bus. Data Bus Busy: Whenever the data is not valid on the bus with DRDY# is deserted, DBSY# is asserted to hold the bus.
DEFER#
1.5V
MAIN
O GTL+
RS[2:0]#
1.5V
MAIN
O GTL+
HTRDY#
1.5V
MAIN
I/O GTL+
DRDY#
1.5V
MAIN
I/O GTL+
DBSY#
1.5V
MAIN
I/O GTL+
Preliminary V.10 Oct.07,1999
24
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset BPRI# 1.5V MAIN O GTL+ Priority Agent Bus Request: BPRI# is driven by the priority agent that wants to request the bus. BPRI# has higher priority than BREQ0# to access a bus. CPURST# 1.5V MAIN O GTL+ Host Bus Reset: CPURST# is used to keep all the bus agents in the same initial state before valid cycles issued. Host Address Bus : Host Data Bus : Floating Point Error : CPU will assert this signal upon a floating point error occurring. Ignore Numeric Error : IGNE# is asserted to inform CPU to ignore a numeric error. Speed Trap for PII : This pin will be forced to voltage level according to the input value of MD41 or APC0h.4 during system reset period. NMI 1.5V~5V MAIN OD Non-Maskable Interrupt : A rising edge on NMI will trigger a non-maskable interrupt to CPU. Speed Trap for PII : This pin will be forced to voltage level according to the input value of MD44 or APC0h.7 during system reset period.
HA[31:3]# HD[63:0]# FERR#
1.5V 1.5V 1.5V~5V
MAIN MAIN MAIN
I/O GTL+ I/O GTL+ I
IGNE#
1.5V~5V
MAIN
OD
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset INTR 1.5V~5V MAIN OD Interrupt Request : High-level voltage of this signal indicates the CPU that there is outstanding interrupt(s) needed to be serviced. Speed Trap for PII : This pin will be forced to voltage level according to the input value of MD43 or APC0h.6 during system reset period. CPUSLP# 1.5V~5V MAIN OD CPU Sleep : SIS630 can optionally assert CPUSLP# to force the CPU into deep sleep mode when going to S2 state. Stop Clock : STPCLK# will be asserted to inhibit or throttle CPU activities upon a pre-defined power management event occurs. System Management Interrupt : SMI# will be asserted when a predefined power management event occurs. Initialization : INIT is used to re-start the CPU without flushing its internal caches and registers. In Pentium II platform it is active high. This signal requires an external pull-up resistor tied to 3.3V.
STPCLK#
1.5V~5V
MAIN
OD
SMI#
1.5V~5V
MAIN
OD
INIT#
1.5V~5V
MAIN
OD
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset A20M# 1.5V~5V MAIN OD Address 20 Mask : When A20M# is asserted, the CPU A20 signal will be forced to " 0" Speed Trap for PII : This pin will be forced to voltage level according to the input value of MD42 or APC0h.5 during system reset period.
4.2
DRAM Controller
Name SDCLK MD[63:0] MA[14:0] CSA[5:0]# CSB[5:0]# DQM[7:0]# WE# SRAS# SCAS# CKE Tolerance 3.3V/5V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Power Plane MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN AUX Type Attr I I/O O O O O O O O O Description SDRAM Clock Input System Memory Data Bus System Memory Address Bus SDRAM Chip Select SDRAM Chip Select (Duplicated Copy) Signals
SDRAM Input/Output Data Mask SDRAM Write Enable SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Clock Enable During Suspend-to-DRAM mode (ACPI S2 or S3 state), SDRAM can be put into self-refresh mode by asserting CKE.
4.3
PCI Interface
Name Tolerance Power Plane Type Attr Description
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Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset PCICLK 3.3V/5V MAIN I PCI Clock : The PCICLK input provides the fundamental timing and the internal operating frequency for the SiS Chip. It runs at the same frequency and skew of the PCI local bus. PCI Bus Command and Byte Enables: PCI Bus Command and Byte Enables define the PCI command during the address phase of a PCI cycle, and the PCI byte enables during the data phases. C/BE[3:0]# are outputs when the SiS Chip is a PCI bus master and inputs when it is a PCI slave. AD[31:0] 3.3V/5V MAIN I/O PCI Address /Data Bus: In address phase: 1.When the SiS Chip is a PCI bus master, AD[31:0] are output signals. 2.When the SiS Chip is a PCI target, AD[31:0] are input signals. In data phase: 1.When the SiS Chip is a target of a memory read/write cycle, AD[31:0] are floating. 2.When the SiS Chip is a target of a configuration or an I/O cycle, AD[31:0] are output signals in a read cycle, and input signals in a write cycle.
C/BE[3:0]#
3.3V/5V
MAIN
I/O
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset PAR 3.3V/5V MAIN I/O Parity : SIS630 drives out Even Parity covering AD[31:0] and C/BE[3:0]#. It does not check the input parity signal. Frame#: FRAME# is an output when the SiS Chip is a PCI bus master. The SiS Chip drives FRAME# to indicate the beginning and duration of an access. When the SiS Chip is a PCI slave device, FRAME# is an input signal. Initiator Ready : IRDY# is an output when the SiS Chip is a PCI bus master. The assertion of IRDY# indicates the current PCI bus master's ability to complete the current data phase of the transaction. For a read cycle, IRDY# indicates that the PCI bus master is prepared to accept the read data on the following rising edge of the PCI clock. For a write cycle, IRDY# indicates that the bus master has driven valid data on the PCI bus. When the SiS Chip is a PCI slave, IRDY# is an input pin.
FRAME#
3.3V/5V
MAIN
I/O
IRDY#
3.3V/5V
MAIN
I/O
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Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset TRDY# 3.3V/5V MAIN I/O Target Ready : TRDY# is an output when the SiS Chip is a PCI slave. The assertion of TRDY# indicates the target agent's ability to complete the current data phase of the transaction. For a read cycle, TRDY# indicates that the target has driven valid data onto the PCI bus. For a write cycle, TRDY# indicates that the target is prepared to accept data from the PCI bus. When the SiS Chip is a PCI master, it is an input pin. Stop# : STOP# indicates that the bus master must start terminating its current PCI bus cycle at the next clock edge and release control of the PCI bus. STOP# is used for disconnection, retry, and targetabortion sequences on the PCI bus.
STOP#
3.3V/5V
MAIN
I/O
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset DEVSEL# 3.3V/5V MAIN I/O Device Select : As a PCI target, SiS Chip asserts DEVSEL# by doing positive or subtractive decoding. SiS Chip positively asserts DEVSEL# when the DRAM address is being accessed by a PCI master, PCI configuration registers or embedded controllers' registers are being addressed, or the BIOS memory space is being accessed. The low 16K I/O space and low 16M memory space are responded subtractively. The DEVESEL# is an input pin when SiS Chip is acting as a PCI master. It is asserted by the addressed agent to claim the current transaction. PCI Lock : When PLOCK# is sampled asserted at the beginning of a PCI cycle, SIS630 considers itself being locked and remains in the locked state until PLOCK# is sampled and negated at the following PCI cycle. PCI Bus Request : PCI Bus Master Request Signals PCI Bus Grant : PCI Bus Master Grant Signals PCI interrupt A,B,C,D : The PCI interrupts will be connected to the inputs of the internal Interrupt controller through the rerouting logic associated with each PCI interrupt.
PLOCK#
3.3V/5V
MAIN
I/O
PREQ[2:0]# PGNT[2:0]# INT[A:D]#
3.3V/5V 3.3V 3.3V/5V
MAIN MAIN MAIN
I O I
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset PCIRST# 3.3V AUX O PCI Bus Reset : PCIRST# will be asserted during the period when PWROK is low, and will be kept on asserting until about 24ms after PWROK goes high. System Error : When sampled active low, a nonmaskable interrupt (NMI) can be generated to CPU if enabled.
SERR#
3.3V/5V
MAIN
I
4.4
PCI IDE Interface
Name IDA[15:0] IDB[15:0] Tolerance 3.3V/5V 3.3V/5V 3.3V 3.3V 3.3V 3.3V 3.3V/5V 3.3V/5V 3.3V 3.3V/5V 3.3V 3.3V Power Plane MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN MAIN Type Attr I/O I/O O O O O I I O I O O Description Primary Channel Data Bus Secondary Channel Data Bus Primary Channel CS[1:0] Secondary Channel CS[1:0] Primary/Secondary Channel IOR# Signals Primary/Secondary Channel IOW# Signals Primary/Secondary ICHRDY# Signals Channel
IDECSA[1:0]# IDECSB[1:0]# IIOR[A:B]# IIOW[A:B]# ICHRDY[A:B] IDREQ[A:B] IDACK[A:B]# IIRQ[A:B] IDSAA[2:0] IDSAB[2:0]
Primary/Secondary Channel DMA Request Signals Primary/Secondary DMACK# Signals Primary/Secondary Interrupt Signals Channel Channel
Primary Channel Address [2:0] Secondary Channel Address [2:0]
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset CBLID[A:B] 3.3V/5V MAIN i Primary/Secondary Ultra-66 Cable ID
4.5
VGA Interface
Name HSYNC VSYNC SSYNC DDCCLK Tolerance 3.3V 3.3V 3.3V 3.3V/5V 3.3V/5V Power Plane MAIN MAIN MAIN MAIN MAIN MAIN Type Attr O O O I/O I/O AI Description Horizontal Sync Vertical Sync Stereo Sync Display Data Channel Clock Line Display Data Channel Data Line Compensation Pin: Connect this pin to AVDD via a 0.1uF capacitor Reference Resistor: An external resistor is connected between the RSET pin and AGND to control the magnitude of the full-scale current. Voltage Reference: Connect 0.1uF Capacitor to Ground. VGA Frame Buffer Cache Chip Select Red Signal Output Green Signal Output Blue Signal Output
DDCDATA COMP
RSET
MAIN
AI
VREF VCS# ROUT GOUT BOUT 3.3V
MAIN MAIN MAIN MAIN MAIN
AI I/O AO AO AO
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset VBA1 VBCLK PLPWDN# 3.3V MAIN O I/O O Display Memory Bank Select: When 128bits DRAM interface enable, it represents the Memory Bank Select Digital Video Clock Input: When Video Bridge connected, it represents the Digital Video Clock Input Panel Power Down When external LCD transmitter connected, it represents power down. VMA11 VGCLK 3.3V MAIN O O Display Memory Address bit 11 When 128bits DRAM interface enable, it represents the Memory Address bit 11 Digital Video Clock Output: When Video Bridge connected, it represents the Digital Video Clock Output VMA10 VBHCLK 3.3V MAIN O O Display Memory Address bit 10 When 128bits DRAM interface enable, it represents the Memory Address bit 10 Control Clock Output: When Video Bridge connected, represents the Control Clock Output VMD[63:60] VMD[59:52] VBRGB[7:0] VMD[51:49] VBRGB[18:16] VMD[48:44] VBRGB[19:23] VMD[43:42] VBRGB[10:11] 3.3V 3.3V MAIN MAIN I/O I/O O I/O O I/O O I/O O Display Memory Data Bus bits [63:60] Display Memory Data Bus bits [59:52] Digital Video Data bits [7:0] Display Memory Data Bus bits [51:49] Digital Video Data bits [18:16] Display Memory Data Bus bits [48:44] Digital Video Data bits [19:23] Display Memory Data Bus bits [43:42] Digital Video Data bits [10:11] it
3.3V
MAIN
3.3V
MAIN
3.3V
MAIN
Preliminary V.10 Oct.07,1999
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset VMD[41:40] VBRGB[9:8]] VMD[39:38] VBRGB[13:12] VMD[37:36] VBRGB[14:15] VMD35 VBBLANKN VMD[34:33] TVCTL[0:1] VMD32 VBCAD VMD31 VBHSYNC VMD30 VBVSYNC VMD29 DDC2CLK VMD28 DDC2DATA VMD[27:0] VDQM[7:0] OSCI ENTEST 3.3V MAIN I/O O I/O O I/O O I/O O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I I Display Memory Data Bus bits [41:40] Digital Video Data bits [9:8] Display Memory Data Bus bits [39:38] Digital Video Data bits [13:12] Display Memory Data Bus bits [37:36] Digital Video Data bits [14:15] Display Memory Data Bus bit 35 Digital Video Display Enable Display Memory Data Bus bits [34:33] Video Bridge Data Control bits [0:1] Display Memory Data Bus bit 32 Video Bridge Programming Control Display Memory Data Bus bit 31 Digital Video Horizontal Sync Display Memory Data Bus bit 30 Digital Video Vertical Sync Display Memory Data Bus bit 29 Second Display data channel clock line Display Memory Data Bus bit 28 Second Display data channel data line Display Memory Data Bus bits [27:0] Display Memory SDRAM Input /Output Mask External 14.318MHz Clock Input Test Mode Enable
3.3V
MAIN
3.3V
MAIN
3.3V
MAIN
3.3V
MAIN
3.3V
MAIN
3.3V
MAIN
3.3V
MAIN
3.3V
MAIN
3.3V
MAIN
3.3V 3.3V 3.3V/5V 3.3V/5V
MAIN MAIN MAIN MAIN
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
4.6
Power management Interface
Name ACPILED Tolerance <=5V Power Plane AUX Type Attr OD Description ACPILED : ACPILED can be used to control the blinking of an LED at the frequency of 1 Hz to indicate the system is at power saving mode. I External SMI#: EXTSMI# can be used to generate wakeup event, sleep event, or SCI/SMI#/GPEIRQ event to the ACPI-compatible power management unit. PME# : When the system is in power-down mode, an active low event on PME# will cause the PSON# to go low and hence turn on the power supply. When the system is in suspend mode, an active PME# event will cause the system wakeup and generate an SCI/SMI#/GPEIRQ. ATX Power ON/OFF control: PSON# is used to control the on/off state of the ATX power supply. When the ATX power supply is in the OFF state, an activated power-on event will force the power supply to ON state. Power Button: This signal is from the power button switch and will be monitored by the ACPI-compatible power management unit to switch the system between working and sleeping states.
EXTSMI#
3.3V/5V
MAIN
PME#
3.3V/5V
AUX
I/O
PSON#
<=5V
AUX
OD
PWRBTN#
3.3V/5V
AUX
I
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset RING 3.3V/5V AUX I Ring Indication : An active RING pulse and lasting for more than 4ms will cause a wakeup event for system to wake from S1~S5. Thermal Detect : THERM# is connected to the internal ACPI-compatible power management unit as an indication of outstanding thermal event. An active THERM# event can be used to generate SCI/SMI#/GPEIRQ. If THERM# is activated for more than 2 second, a thermal override event will occur and the system will enter CPU thermal throttling mode automatically. General Purpose Input/Output [6:4]: Refer to GPIO description.
THERM#
3.3V/5V
MAIN
I
GPIO[6:4]
3.3V/5V
AUX
I/O/OD
4.7
SMBus Interface
Name SMBDAT I2CDAT Tolerance 3.3V/5V Power Plane MAIN Type Attr I/OD I/OD Description SMBus Data : SMBus data input/output pin. I2C Data : I2C data input/output pin. SMCLK I2CCLK 3.3V/5V MAIN I/OD I/OD SMBus Clock : SMBus clock input/output pin. I2C Clock : I2C clock input/output pin.
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset SMBALT# I2CALT# GPIO15 3.3V/5V AUX I/OD I/OD I/O/OD SMBus Alert : This pin is used for SMBus device to wake up the system from sleep state or to generate SCI/SMI#/GPEIRQ. I2C Alert : This pin is used for I2C device to wake up the system from sleep state or to generate SCI/SMI#/GPEIRQ. General Purpose Input/Output 15 : Refer to GPIO description.
4.8
Keyboard controller Interface
Name Tolerance 3.3V/5V Power Plane AUX Type Attr I/OD I/O/OD Description Keyboard Dada : When the internal keyboard controller is enabled, this pin is used as the keyboard data signal. General Purpose Input/Output 10 : Refer to GPIO description.
KBDAT GPIO10
KBCLK GPIO11
3.3V/5V
AUX
I/OD I/O/OD
Keyboard Clock : When the internal keyboard controller is enabled, this pin is used as the keyboard clock signal. General Purpose Input/Output 11 : Refer to GPIO description.
PMDAT GPIO12
3.3V/5V
AUX
I/OD I/O/OD
PS2 Mouse Data: When the internal keyboard and PS2 mouse controllers are enabled, this pin is used as PS2 mouse data signal. General Purpose Input/Output 12 : Refer to GPIO description.
Preliminary V.10 Oct.07,1999
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset PMCLK GPIO13 3.3V/5V AUX I/OD I/O/OD PS2 Mouse Clock: When the internal keyboard and PS2 mouse controllers are enabled, this pin is used as the PS2 mouse clock signal. General Purpose Input/Output 13 : Refer to GPIO description. KLOCK# GPIO14 3.3V/5V AUX I I/O/OD Keyboard Lock: When KLOCK# is tied low, the internal keyboard controller will not respond to any key-strikes. General Purpose Input/Output 14 : Refer to GPIO description.
4.9
LPC Interface
Name LAD[3:0] Tolerance 3.3V/5V Power Plane MAIN Type Attr I/O Description LPC Address/Data Bus : LPC controller drives these four pins to transmit LPC command, address, and data to LPC device. LPC DMA Request 0: This pin is used by LPC device to request DMA cycle. LPC Frame : This pin is used to notify LPC device that a start or a abort LPC cycle will occur. Serial IRQ : This signal is used as the serial IRQ line signal.
LDRQ#
3.3V/5V
MAIN
I
LFRAME#
3.3V
MAIN
O
SIRQ
3.3V/5V
MAIN
I/OD
4.10
RTC Interface
Name Tolerance Power Plane Type Attr Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset AUXOK 1.8V RTC I Auxiliary Power OK : This signal is supplied from the power source of resume well. It is also used to reset the logic in resume power well. If there is no auxiliary power source on the system, this pin should be tied together with PWROK. Battery Power OK: When the internal RTC is enabled, this signal is used to indicate that the power of RTC well is stable. It is also used to reset the logic in RTC well. If the internal RTC is disabled, this pin should be tied low. RTC 32.768 KHz Input : When internal RTC is enabled, this pin provides the 32.768 KHz clock signal from external crystal or oscillator. RTC 32.768 KHz Output : When internal RTC is enabled, this pin should be connected with the other end of the 32.768 KHz crystal or left unconnected if an oscillator is used. Main Power OK : A high-level input to this signal indicates the power being supplied to the system is in stable operating state. During the period of PWROK being low, CPURST and PCIRST# will all be asserted until after PWROK goes high for 24 ms.
BATOK
1.8V
RTC
I
OSC32KHI
1.8V
RTC
I
OSC32KHO
<1.8V
RTC
O
PWROK
1.8V
RTC
I
4.11
AC' 97 interface
Name Tolerance Power Plane Type Attr Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset AC_BITCLK 3.3V/5V MAIN I AC' 97 Bit Clock : This signal is a 12.288MHz serial data clock, which is generated by primary Codec. AC' 97 Reset : Hardware reset signal for external Codecs. AC' 97 Serial Data input : Serial data input from primary Codec and secondary Codec. AC' 97 Serial Data output : Serial data output to Codecs. AC' 97 Syncronization : This is a 48KHz signal, which is used to syncronize the Codecs. S/PDIF Transmitter Output General Purpose Input/Output 7 : Refer to GPIO description.
AC_RESET#
3.3V
AUX
O
AC_SDIN[1:0]
3.3V/5V
AUX
I
AC_SDOUT AC_SYNC
3.3V 3.3V
MAIN MAIN
O O
SPDIF GPIO7
3.3V/5V
MAIN
O I/O/OD
4.12
Fast Ethernet and Homenetworking interface
Tolerance 3.3V Power Plane AUX Type Description Attr O Serial EEPROM Chip Select : This enables the EEPROM during loading of the Ethernet configuration data. O Serial EEPROM Data Input : During serial EEPROM access cycle, the SIS630 will use this pin to serially write OP codes, addresses and data into the serial EEPROM.
Name EECS
EEDI
3.3V
AUX
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset EEDO GPIO3 3.3V/5V AUX I Serial EEPROM Data Output : I/O/OD During serial EEPROM access cycle, the SIS630 will read the contents of the EEPROM serially through this pin. Requires external pull-up resistor. General Purpose Input/Output 3 : Refer to GPIO description. EESK 3.3V AUX O Serial EEPROM Clock : This pin provides the clock for the serial EEPROM. PHY 25MHz Clock Input : This pin is supplied the 25MHz clock signal input from the external crystal or an oscillator.
OSC25MHI
3.3V
AUX
I
PLEDO# OC3# GPIO8
3.3V
AUX
OD Programmable LED Output : O (A)Select 10/100Mbps LAN Mode: I/O/OD This pin is used as an LINK/ACTIVITY indication output. (B)Select Home Networking Mode: This pin is also an LINK/ACTIVITY indication output. OC3# : When this pin is configured as OC3#, it can detects USB Port 3 over current condition. General Purpose Input/Output 8 : Refer to GPIO description.
REXT
AUX
I
Transmit Current Set : An external resistor connected between this pin and GND will set the output current level for the twisted pair outputs. Twisted Pair Receive Positive Input Twisted Pair Receive Negative Input Twisted Pair Transmit Positive Output Silicon Integrated Systems Corporation
TPIP TPIN TPOP Preliminary V.10 Oct.07,1999
AUX AUX AUX 42
I I O
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset TPON HRTXRXP HRTXRXN AUX AUX AUX O I/O I/O Twisted Pair Transmit Negative Output Twisted Pair Transmit / Receive Positive Data Twisted Pair Transmit / Receive Negative Data
4.13
USB interface
Tolerance 3.3V/5V Power Plane MAIN Type Attr I Description USB 48 MHz clock input : This signal provides the fundamental clock for the USB Controller.
Name CLK48M
OC0# PCIREQ3# GPIO0
3.3V/5V
MAIN
I USB Port 0 Over Current Detection : I OC0# is used to detect the over current I/O/OD condition of USB Port 0. External PCI Master Request 3: PCIREQ3# is used for PCI Device on PCI Slot 3 to assert its request to hold PCI Bus. General Purpose Input/Output 0 : Refer to GPIO description.
OC1# PCIGNT3# GPIO1
3.3V/5V
MAIN
I USB Port 1 Over Current Detection : O OC1# is used to detect the over current I/O/OD condition of USB Port 1. External PCI Master Grant 3 : PCIGNT3# is used to indicate PCI Device on PCI Slot 3 the PCI Bus has been granted. General Purpose Input/Output 1 : Refer to GPIO description.
Preliminary V.10 Oct.07,1999
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset OC3# LDRQ1# GPIO2 3.3V/5V MAIN I USB Port 3 Over Current Detection: I OC3# is used to detect the over current I/O/OD condition of USB Port 3. LPC DMA Request 1 : LDRQ1# is the second LPC DMA request signal used by LPC Device to request DMA cycles. General Purpose Input/Output 2 : Refer to GPIO description. USBP[4:0]P USBP[4:0]N 3.3V 3.3V AUX AUX I/O I/O USB Port [4:0] Positive Input/Output USB Port [4:0] Negative Input/Output
4.14
Legacy I/o and Miscellaneous Signals
Name SPK Tolerance 3.3V Power Plane MAIN Type Attr O Description Speaker output : The SPK is connected to the system speaker.
4.15
Power and Ground Signals
Tolerance Power Plane GROUND MAIN AUX AUX AUX RTC MAIN MAIN AUX AUX 44 Type Attr Description 0V 1.8V 1.8V 3.3V 3.3V 1.8V 3.3V 3.3V 3.3V 3.3V Silicon Integrated Systems Corporation
Name VSS IVDD IVDD (AUX) OVDD (AUX) USBVDD RTCVDD DCLKAVDD ECLKAVDD TXAVDD RXAVDD
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset DACAVDD IDEAVDD SDAVDD CPUAVDD VTTB VSSQ VTTA VCC3 MAIN MAIN MAIN MAIN MAIN GROUND MAIN MAIN 3.3V 1.8V 3.3V 3.3V 1.5V 0V 1.5V 3.3V
Preliminary V.10 Oct.07,1999
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
5
Hardware Trap
There are some pins used for trapping purpose to identify the hardware configurations at the power-up stage. These pins will be recognized as " 1" if pull-up resistors are used; and will be recognized as " 0" if pull-down resistors are used. The following table is a summary of all the Hardware Trap pins in SIS630. Symbol MD62 Description PCI Clock PLL Circuit Enable Pull-up: Disable Pull-down: Enable (recommended) MD61 SDRAM Clock DLL Circuit Enable Pull-up: Disable Pull-down: Enable (recommended) MD60 CPU Clock DLL Circuit Enable Pull-up: Disable Pull-down: Enable (recommended) MD[59:58] MD[57:56] MD[55:54] MD49 SDRAM Clock DLL ER[1:0] CPU Clock DLL ER[1:0] PCI Clock PLL ER[1:0] High : internal control output Low : internal clock output MD48 MD44
Output internal signals from XVDQM
PII CPU Speed Trap for NMI The voltage level on this pin will be forwarded to NMI during CPURST period and last 7 PCICLK after CPURST is deasserted. It is used to determine PII CPU Core/Bus frequency ratio. PII CPU Speed Trap for INTR 46 Silicon Integrated Systems Corporation
MD43 Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset The voltage level on this pin will be forwarded to INTR during CPURST period and last 7 PCICLK after CPURST is deasserted. It is used to determine PII CPU Core/Bus frequency ratio. MD42 PII CPU Speed Trap for A20M# The voltage level on this pin will be forwarded to A20M# during CPURST period and last 7 PCICLK after CPURST is deasserted. It is used to determine PII CPU Core/Bus frequency ratio. PII CPU Speed Trap for IGNE# The voltage level on this pin will be forwarded to IGNE# during CPURST period and last 7 PCICLK after C PURST is deasserted. It is used to determine PII CPU Core/Bus frequency ratio. Enable/Disable System Auto-Reset Function If the auto-reset function is enabled, PCIRST# will be asserted every 5~6 seconds unless the software disables the function by writing a zero to ACPI56h.6. Low: Enable High: Disable MD38 VGA Interrupt Function Enable Pull-up: Enable Pull-down: Disable MD37 External CLKGEN Enable Pull-up: Use External Clock Pull-down: Use Internal Clock MD36 Panel Link Enable (Note 2) Pull-up: Enable Panel Link Pull-Down: Disable Panel Link(default) MD35 Preliminary V.10 Oct.07,1999 47 VGA Multi-Function Select Silicon Integrated Systems Corporation
MD41
MD40
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Pull-up: Select Function 1 Pull-Down: Select Function 0 MD34 VGA Multi-Function Enable Pull-up: Enable Pull-Down: Disable MD33 Video Bridge Enable (Note 2) Pull-up: Enable Pull-down: Disable MD32 PAL/NTSC Select Pull-up: Select PAL system Pull-Down: Select NTSC system Note: There are internal pull-down resistors on MD lines. MD36 0 0 1 1 MD33 0 1 0 1 FBC Enable SiS301 Video Bridge The 3rd Party Panel Link Chip is used TV Encoder Function
Preliminary V.10 Oct.07,1999
48
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
6
6.1
6.1.1
Function Description
MA Mapping Table
SDRAM/System Memory
SDRAM TYPE DIMM SDM
chip
(NBAXNRAXNC )
A
1X11 1X13 2X12 2X13 1X11 1X13 2X12 2X13 1X11 1X13 2X12 2X13 2X11 1X13 2X12 2X13 X8 X8 X8 X8 X9 X9 X9 X9 X10 X10 X10 X10 X8 X11 X11 X11
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
MA0 MA0 MA1 MA1 MA2 MA2 MA3 MA3 MA4 MA4 MA5 MA5 MA6 MA6 MA7 MA7 MA8 MA8 MA9 MA9 MA10 AP MA11 BA0 MA12 BA1 MA13 MA11 MA14 MA12
3 4 5 6 7 8 9
3 4 5 6 7 8 9
3 4 5 6 7 8 9
3 4 5 6 7 8 9
3 4 5 6 7 8 9
23#/ 23
3 4 5 6 7 8 9 23
3 4 5 6 7 8 9 23
3 4 5 6 7 8 9 23
3 4 5 6 7 8 9 23
24#/ 24
3 4 5 6 7 8 9 23 24 [0] 11 [0]
3 4 5 6 7 8 9 23 24 [0] 11 12
3 4 5 6 7 8 9 23 24 [0] 11 12
3 4 5 6 7 8 9
3 4 5 6 7 8 9 23 24
3 4 5 6 7 8 9 23 24 [0] 11 12
27
3 4 5 6 7 8 9 23 24 [0] 11 12 27
10@ 10@ 10@ 10@ 10@ 10@ 10@ 10@ 10@ 10@ 10@ 10@ 10@ 10@ 10@ 10@
[0] 11 [0]
[0] 11 [0]
[0] 11 12
[0] 11 12
[0] 11 [0]
[0] 11 [0]
[0] 11 12
[0] 11 12
[0] 11 [0]
[0] 11 12
[0] 11 [0]
27
27#/ 27#/
SIDE-MA (SINGLE/ [0]/12 DOUBLE)
[0]/12
[0]/13
[0]/13
[0] /12
[0]/ 12
[0]/13
[0]/13
[0]/12
[0]/12
[0]/13 [0]/ 13
[0]/13
[0]/12
[0]/13
[0]/13
DIMM SDM RA chip
RA
RA
RA
RA
RA
RA
RA
RA
RA
RA
RA
RA
RA
RA
RA
Preliminary V.10 Oct.07,1999
49
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset MA0 MA0 13 MA1 MA1 14 MA2 MA2 15 MA3 MA3 16 MA4 MA4 17 MA5 MA5 18 MA6 MA6 19 MA7 MA7 20 MA8 MA8 21 MA9 MA9 MA10 AP MA11 BA0 MA12 BA1 MA13 MA11 MA14 MA12
22#/22
13 14 15 16 17 18 19 20 21 22
5#
13 / 13 / 13 25# 26# 14 15 16 17 18 19 20 21 22 14 15 16 17 18 19 20 21 22
23
13 14 15 16 17 18 19 20 21 22
6#
13 / 13 / 13 26# 27# 14 15 16 17 18 19 20 21 22
25
13 14 15 16 17 18 19 20 21 22
7#
13 / 13 / 13 / 13 27# 28# 24# 14 15 16 17 18 19 20 21 22 14 15 16 17 18 19 20 21 22
27
13 / 13 / 28# 29# 14 15 16 17 18 19 20 21 22 14 15 16 17 18 19 20 21 22
25
14 15 16 17 18 19 20 21 22
4#
14 15 16 17 18 19 20 21 22
14 15 16 17 18 19 20 21 22
5#
14 15 16 17 18 19 20 21 22
23
14 15 16 17 18 19 20 21 22
8#
12/2 12/2 23 3#
12/2 12/2 25#/ 25
12/2 12/2 25
27#/ 23#/ 12/2 25
11 [0]
11 [0]
11 12
11 12
11 [0]
11 [0] 24 25#/ 25
11 12 24
11 12 26#/ 26 24
11 [0]
11 [0]
11 12
11 12
11 12
11 [0] 26 25
11 12 26
11 12 26 28#/ 28
24#/ 24#/ 24 24 24 23
32MB {0010}
26#/ 26#/ 26 26 27 25 25
25#/ 25
64MB 16MB {0011} {0100}
Rank Size 8MB 32MB System Reg.{0000} {0001}
64MB 64MB 128MB 32MB 128MB 128MB 256MB 16MB 256MB 256MB 512MB {0101} {0110} {0111} {1000} {1001} {1010} {1011} {1100} {1101} {1110} {1111}
Note: 1.@ for page hit comparator, #for rank decoder. 2. Constant Page Size: 2K byte (4Kbyte for GUI-128 BIT ACCESS) 3. A1.2:A1 for single sided DIMM, A2 for double-sided DIMM.
6.1.2 TYPE
DIMM
SDRAM/FBC SDRAM
(NBAXNRAXNCA)
1x9x8 1x10x8 CA 1X11X8 CA 2X12X8 CA 1X11X9 CA 1X11X10 CA 2X11X8 1X12X8 CA CA
SDM chip
CA 3 4 5 6 7 8
MA0 MA1 MA2 MA3 MA4 MA5
MA0 MA1 MA2 MA3 MA4 MA5
3 4 5 6 7 8
3 4 5 6 7 8 50
3 4 5 6 7 8
3 4 5 6 7 8
3 4 5 6 7 8
3 4 5 6 7 8
3 4 5 6 7 8
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset MA6 MA7 MA8 MA9 MA6 MA7 MA8 MA9 [0] 11 [0] [0] 11 [0] [0] 11 [0] [0] 11 12 [0] 11 [0] 9 10@ 9 10@ 9 10@ 9 10@ 9 10@ 23# 9 10@ 23 24# [0] 11 [0] [0] 11 12 [0] 11 [0] 9 10@ 9 10@
MA10 AP MA11 BA0 MA12 BA1 MA13 MA11 MA14 MA12
DIMM MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 SDM chip MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 AP BA0 BA1 MA11 MA12
RA 13 14 15 16 17 18 19 20#
RA 13 14 15 16 17 18 19 20 21#
RA 13 14 15 16 17 18 19 20 21 22#
RA 13 14 15 16 17 18 19 20 21 22 23 11 12 24#
RA 13 14 15 16 17 18 19 20 21 22 12 11 [0]
RA 13 14 15 16 17 18 19 20 21 22 12 11 [0]
RA 13 14 15 16 17 18 19 20 21 22 23# 11 12
RA 13 14 15 16 17 18 19 20 21 22 12 11 [0] 23#
12 11 [0]
12 11 [0]
12 11 [0]
Rank Size 2MB 4MB 8MB 32MB 16MB 32MB 16MB 16MB System Reg. {0000} {0001} {0010} {0011} {0100} {0101} {0110} {0111} Note: 1. Additional Configurations:1x9x8, 1x10x8, 1x12x8, and the other configurations are the same as system configurations 2.Additional PinS for 128-bit solution are " GUI_AP" ,"GUI_BA1" ," GUI_MA11"
6.1.3
VCM/System Memory 51 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset VC SDRAM TYPE (NBAXNRAXNCAXNSA)
1X13X6X2 CA MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8(CH0) MA9(CH1) MA10/AP MA11/BA0(BA) MA12/BA1 MA13/MA11(CH2) MA14/MA12(CH3) 3 4 5 6 7 8@ 1X13X7X2 CA 3 4 5 6 7 8 9@ 1X13X8X2 CA 3 4 5 6 7 8 9 10@
(9)* (10)*
(10)*
[0] [0] [0]
[0] [0] [0]
[0] [0] [0]
SA MA0(SEG0) MA1(SEG1) MA2 MA3 MA4 MA5 MA6 MA7 MA8(CH0) MA9(CH1) MA10/AP MA11/BA0(BA) MA12/BA1 MA13/MA11(CH2) MA14/MA12(CH3) 11 12
SA 11 12
SA 11 12
[1]
13
[1]
13
[1]
13
MA-CS
[0] /14 52
[0] /14
[0]/14
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
RA MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10/AP MA11/BA0 MA12/BA1 MA13/MA11 MA14/MA12 14 / 25 10 14 / 26 10 14 / 27 26 15 16 17 18 19 20 21 22 23 24 9 13 RA 15 16 17 18 19 20 21 22 23 24 25 13 RA 15 16 17 18 19 20 21 22 23 24 25 13
Rank/DIMM Size System Reg.
32MB {0000}
64MB {0001}
128MB {0010}
Note: 1.@ for boundary page hit comparator, #for rank decoder. Page Size is programmable (0.5k, 1k, 2k), and constant for all vc-sdram rank. 2.A1/A2: A1 for single sided DIMM or 128-bit mode, A2 for double-sided & 64-bit mode.
Preliminary V.10 Oct.07,1999
53
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 6.1.4 VCM/FBC
SA 1X13X6X2 CA MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8(CH0) MA9(CH1) MA10/AP MA11/BA0(BA) MA12/BA1 MA13/MA11(CH2) MA14/MA12(CH3) 3 4 5 6 7 8 MA0(SEG0) MA1(SEG1) MA2 MA3 MA4 MA5 MA6 MA7 MA8(CH0) MA9(CH1) MA10/AP MA11/BA0(BA) 11 12 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 RA 15 16 17 18 19 20 21 22 23 24 9 13
VC SDRAM TYPE
(9)* (10)*
[1]
13
MA10/AP MA11/BA0 MA12/BA1 MA13/MA11 MA14/MA12
[0] [0] [0]
MA12/BA1 MA13/MA11(CH2) MA14/MA12(CH3) MA14/MA12(CH3)
14 10
GUI Size: 32MB GUI Reg. {0000}
Preliminary V.10 Oct.07,1999
54
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
6.2
PSON# and ACPILED Description
Pin Name PSON# Buffer Type Auxiliary / Open Drain Description PS_ON# is an active low signal that turns on all of the main power rails. When a power-up event occurs, SIS630 would assert PSON# to turn on the power supply. When a power-down event occurs, SIS630 would deassert PSON# to turnoff the power supply. This signal should be held at +5VDC by a pullup resistor internal to the power supply.
Preliminary V.10 Oct.07,1999
55
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
AC_SDIN[0]
CODEC0_S5WAK_EN APC 06h[6] AUDPME_S5WAK_STS ACPI 61[2]
AC_SDIN[1]
CODEC1_S5WAK_EN APC 06h[7] AUDPME_S5WAK_STS ACPI 61[2]
AUDIO_PME#
AUDPME_S5WAK_EN APC 06h[5] AUDPME_S5WAK_STS ACPI 61[2]
KBC (password)
KBPS_S5WAK_EN APC 05h[2] KBC_S5WAK_STS ACPI 61[1]
KBC (hotkey)
KBHK_S5WAK_EN APC 05h[2] KBC_S5WAK_STS ACPI 61[1]
PWRBTN# RTC_IRQ8
RTC_S5WAK_EN APC 05h[7] PWRBTN_S5WAK_STS ACPI 61[7]
PSON#
RTC_S5WAK_STS ACPI 61[6]
RING
RING_S5WAK_EN APC 05h[6] RING_S5WAK_STS ACPI 61[5]
PCIPME#
PCIPME_S5WAK_EN APC 05h[4] RING_S5WAK_STS ACPI 61[3]
MACPME#
PCIPME_S5WAK_EN APC 05h[5] RING_S5WAK_STS ACPI 61[4]
I2CALT# SMBALT#
SMBALT_S5WAK_EN APC 05h[3] SMBALT_S5WAK_STS ACPI 60[7]
Figure 6.2-1 PSON# Pin Name ACPILED Buffer Type Auxiliary/ Open Drain Description ACPILED is used to denote that the computer is in the sleep mode.
Preliminary V.10 Oct.07,1999
56
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 6.2.1 ACPI
Register 62h~63h System Wakeup form S3/S4/S5 Control Register (S5WAK_CNT) Default Value: 0000h Access: Read/Write
AUX5V
330
SIS630
ACPILED
Figure 6.2-2 ACPILED 7:6 RO ACPILED Output State Control The output state of ACPILED can be controlled by the following combination when system is in S0/S1/S2/S3 states. If the system is in S4/S5 state, ACPILED will be set to high impedance. 00 : Output low 01 : Blink 10 : High impedance 11 : Reversed
Preliminary V.10 Oct.07,1999
57
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
6.3
Power States for SIS630 Signals
Term In Fixed Driven -Running High Low Defined Off High-Z Pin Type Input Input Input Input Input/Output Input/Output Input/Output Output Output Output The pin is driven by external resistors. The logic value is allowed tobe changed. The logic value of the input pin is independent of PCIRST#. Clocks. SIS630 drives the pin to a logic high level, or the pin is driven to a high logic level by external components. SIS630 drives the pin to a logic low level, or the pin is driven to a low logic level by external components.. SIS630 drives the pin to a logic level, that depends on the function. The output buffer is powered off. The output buffer is high impedence. Description When PCIRST# is asserted, the I/O pin will be set to input mode.
Signal Name
Buffer Type I I I I/O I/O I/O I/O I/O I/O I/O I/O O
Power Plane Core Core Core Core Core Core Core Core Core Core Core Resume
During After PCIRST# PCIRST# PCI Interface Running --High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Running --High High High-Z High-Z High-Z High-Z High-Z Low
S1
S3
S4/S5
PCICLK SERR# INT[A:D]# AD[31:0] C/BE[3:0]# FRAME# IRDY# TRDY# DEVSEL# STOP# PAR PCIRST#
Running High Driven High-Z High-Z High-Z High-Z High-Z High-Z High-Z Low High
Low Low Low Off Off Off Off Off Off Off Off Low
Low Low Low Off Off Off Off Off Off Off Off Low
Low High CPU Interface 58
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset OPURST# INIT# A20M# SMI# STPCLK# CPUSLP# INTR NMI IGNE# FERR# PWRBTN# EXTSMI# RING PME# PSON# CKE THERM# ACPILED OD OD OD OD OD OD OD OD OD I I I I I OD O I OD Core Core Core Core Core Core Core Core Core Core Resume Core Resume Resume Resume Resume Core Resume Low High-Z Defined High-Z High-Z High-Z Defined Defined Defined -ACPI Driven Driven Driven Driven Low High Driven Defined SM Bus High-Z Driven Driven Driven Driven Low High Driven Defined Driven Driven Driven Driven Low High Driven Defined Driven Low Driven Driven High Low Low Define d Off Off Off Off Low Driven Low Driven Driven High High Low High-Z Keep Low 10ns High-Z High-Z High-Z High-Z High-Z Low Low High-Z -High High-Z High-Z High-Z Low High-Z Low Low High-Z High Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off Off
SMBDAT SMBCLK LAD[3:0] LFRAME# LDRQ# SIRQ OSC32KHI OSC32KHO PWROK AUXOK BATOK
I/OD I/OD I/O O I I/O I O I I I
Core Core Core Core Core Core RTC RTC RTC RTC RTC
High-Z
High-Z High-Z High High High
Off Off Off Off Low Off
Running Running
High-Z High-Z LPC Interface High High -High High --
High-Z High-Z High-Z Off RTC Running Running Running Running Running High High Running High High Running High High Running Low High High
Low High High
High High High Audio Modem Interface 59
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset AC_RESET# AC_SYNC AC_CLK AC_SDOUT AC_SDIN[1:0]
OSC25MHI
O O I O I I I I/O I/O I O O I I O O O I/O I/O I O I I/O I I I/O O I I/O I I I/O
Resume Core Core Core Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Resume Core Core Core Core
Low Low -Low
Low Low -Low
Defined Low Low Low Driven Running High-Z High-Z High Defined Defined Driven Driven Low Low Low High-Z High-Z Running Low Running Defined High High Defined High High Defined High High Defined
Low Off Low Off Driven
Running
Low Off Low Off Driven
Running
Driven Driven PHY Interface Running High-Z High-Z High Defined Defined Driven Driven Low Low
Running
CLK25M HRTXRXP HRTXRXN REXT TPO+ TPOTPI+ TPIEECS EEDI EESK UV+[4:0] UV-[4:0] CLK48M SPK CLK14M GPIO0 PCIREQ3# OC0# GPIO1 PCIGNT3# OC1# GPIO2 LDRQ1# OC3# GPIO3
High-Z High-Z High Defined Defined Driven Driven Low Low
High-Z High-Z High
Defined Defined
High-Z High-Z High
Defined Defined
Driven Driven Low Low Low High-Z High-Z Low Off Off Off Off Off Off Off Off Off Low Off Off
Driven Driven Low Low Low High-Z High-Z Low Off Off Off Off Off Off Off Off Off Low Off Off
Low Low USB Interface High-Z High-Z High-Z High-Z Running Running Legacy I/O Low Running In -High In High Hgh In High High In 60 Low Running GPIO In -High In High High In High High In
Core
Core
Resume
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset EEDO GPIO4 GPIO5 GPIO6 GPIO7 SPDIF GPIO8 PLED0# OC2# GPIO10 KBDAT GPIO11 KBCLK GPIO12 PMDAT GPIO13 PMCLK GPIO14 KLOCK# GPIO15 SMBALT# I2CALT# I I/O I/O I/O I/O O I/O OD I I/O I/O D I/O I/O D I/O I/O D I/O I/O D I/O I I/O I I Resume Resume Resume Core Resume -In In In In Low In Defined High In Driven In Driven In Driven In Driven In Defined In High High -In In In In Low In Defined High In Driven In Driven In Driven In Driven In Defined In High High Driven Defined Defined Defined Defined Low Defined Defined High Defined Driven Defined Driven Defined Driven Defined Driven Defined Defined Defined High High Driven Off Off Off Off Off
Off Defined High
Driven Off Off Off Off Off Off Defined High Off High-Z Off High-Z Off High-Z Off High-Z Off Low Off High High
Resume
Off High-Z Off High-z Off High-Z Off High-Z Off Low Off High High
Resume
Resume
Resume
Resume Resume
Preliminary V.10 Oct.07,1999
61
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
6.4
Arbiter Tree
CPU
PRI47L
0-7
PRI47
0-3
PRI01 PRI01L PRI45
4-7
PRI45L
0.1
PRI0 PRI0L PRI2
2.3
PRI2L PRI4
4.5
PRI4L SIOPRIL
6.7
SIOPRI
0
IDE
1
PCI0
2
USB0
3
PCI1
4
AUDIO
5
USB1
6
MAC
7
SIO
Local Arbiter
SIO0
LPC DMA
SIO1
DDMA
SIO2
PCI2
SIO3
MODEM or PCI3
Figure 6.4-1 Arbiter Tree Note 1: SIO means the System I/O for LPC Bridge. Note 2: PCI3 can issue its request to SIS630 only when modem is disabled.
Preliminary V.10 Oct.07,1999
62
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
6.5
Nand Tree Test Scheme
The Mechanism of NAND Tree
SiS Chip side
Figure 6.5-1 The Mechanism of NAND Tree
MainBoard side
Preliminary V.10 Oct.07,1999
63
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
The Test Scheme of NAND Tree TEST# TESTIN1 TESTIN2 TESTIN3 TESTIN4 TESTOUT P1 passed P2 passed P3 passed P4 passed
Figure 6.5-2 The Test Scheme of NAND Tree Table 6.5-1 NAND Tree List for SIS630 TEST INPUT BALL NAME LIST BXGPIO6, BXGPIO5, BXGPIO4, BXGPIO3, XEESK, XEEDI, BXGPIO9, BXGPIO8, XEECS, XPCIRSTN, XACRSTN, XSDATAI0, XSDATAI1, BXGPIO15, BXGPIO14, BXGPIO13, BXGPIO12, BXGPIO11, BXGPIO10, XACPILED, XPSONN, XPMEN, BXRING, XPWRBTNN, XCKE, BXDP4, BXDM4, BXDP3, BXDM3, BXDP2, BXDM2, BXDP1, BXDM1, BXDP0, BXDM0, XINTAN, XINTBN, XINTCN, XINTDN, XSERRN, BXSMBCLK, XUCLK48M, BXSMBDAT, XSPK, BXLAD3, BXLAD2, BXLAD1, BXLAD0, XLFRAMEN, XLDRQN, BXSIRQ, BXVMD63, BXVMD62, BXVMD61, BXVMD60, BXVMD59, BXVMD58, BXVMD57, BXVMD56, XVCSN, XVDQM7, XVDQM6, XVDQM5, XVDQM4, BXVMD55, BXVMD54, BXVMD53, BXVMD52, BXVMD51, BXVMD50, BXVMD49, BXVMD48, BXVMD47, BXVMD46, BXVMD45, BXVMD44, BXVMD43, BXVMD42, BXVMD41, BXVMD40, BXVMD39, BXVMD38, BXVMD37, BXVMD36, BXVMD35, BXVMD34 , BXVMD33, BXVMD32, XVMA10, XVMA11, XVBA1, BXVMD31, BXVMD30, BXVMD29, BXVMD28, BXVMD27 , BXVMD26, BXVMD25, BXVMD24, XVDQM3, XVDQM2 , XVDQM1, XVDQM0, BXVMD23, BXVMD22, BXVMD21 , BXVMD20, BXVMD19, BXVMD18, BXVMD17, BXVMD16, BXVMD15, BXVMD14, BXVMD13, BXVMD12, BXVMD11, BXVMD10, BXVMD9, BXVMD8, BXVMD7, BXVMD6, BXVMD5, BXVMD4, BXVMD3, BXVMD2, BXVMD1, BXVMD0, XSSYNC, XOSCI, XVSYNC, XHSYNC, BXDDCCLK, BXDDCDAT, BXIDA7, BXIDA8, BXIDA6, BXIDA9, BXIDA5, BXIDA10, BXIDA4, BXIDA11, Preliminary V.10 Oct.07,1999 64 TEST OUTPUT BALL NAME BXEXTSMIN
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset BXIDA3, BXIDA12, BXIDA2, BXIDA13, BXIDA1, BXIDA14, BXIDA0, BXIDA15, BXIAIOWCN, XIADRQ, XIACHRDY, BXIAIORCN, BXIADACK, XIAIRQ, BXIADSA1, BXIADSA0, BXIADSA2, XIACBLID, BXIACSN0, BXIACSN1, BXIDB7, BXIDB8, BXIDB6, BXIDB9, BXIDB5, BXIDB10, BXIDB4, BXIDB11, BXIDB3, BXIDB12, BXIDB2, BXIDB13, BXIDB1, BXIDB14, BXIDB0, BXIDB15, BXIBIOWCN, XIBDRQ, BXIBIORCN, XIBCHRDY, BXIBDACK, BXIBDSA1, BXIBDSA0, BXIBDSA2, BXIBCSN0, BXIBCSN1, XIBIRQ, XIBCBLID, XPCICLK, XSDCLK, BXMD32, BXMD0, BXMD33, BXMD1, BXMD34, BXMD2, BXMD35, BXMD3, BXMD36, BXMD4, BXMD37, BXMD5, BXMD38, BXMD6, BXMD39, BXMD7, BXMD40, BXMD8, BXMD41, BXMD9, BXMD42, BXMD10, BXMD43, BXMD11, BXMD44, BXMD12, BXMD45, BXMD13, BXMD46, BXMD14, BXMD47, BXMD15, XSCASN, XRAMWN, XDQM4, XDQM0, XDQM5, XDQM1, XSRASN, XCSNA5, XCSNA4, XCSNA3, XCSNA2, XCSNA1, XCSNA0, XMA0, XMA1, XMA2, XMA3, XMA4, XMA5, XMA6, XMA7, XMA8, XMA9, XMA10, XMA11, XMA12, XMA13, XMA14, XCSNB5, XCSNB4, XCSNB3, XCSNB2, XCSNB1, XCSNB0, XDQM6, XDQM2, XDQM7, XDQM3, BXMD48, BXMD16, BXMD49, BXMD17, BXMD50, BXMD18, BXMD51, BXMD19, BXMD52, BXMD20, BXMD53, BXMD21, BXMD54, BXMD22, BXMD55, BXMD23, BXMD56, BXMD24, BXMD57, BXMD25, BXMD58, BXMD26, BXMD59, BXMD27, BXMD60, BXMD28, BXMD61, BXMD29, BXMD62, BXMD30, BXMD63, BXMD31, BXRSN1, BXRSN2, BXADSN, BXDBSYN, BXHITN, BXHITMN, BXRSN0, BXHREQN3, BXDRDYN, BXHREQN2, XHLOCKN, BXDEFERN, BXHREQN4, BXHTRDYN, BXHREQN1, BXBPRIN, BXHREQN0, BXBNRN, BXHAN4, BXHAN6, BXHAN9, BXHAN3, BXHAN5, BXHAN7, BXHAN10, BXHAN8, BXHAN12, BXHAN14, BXHAN13, BXHAN11, BXHAN16, BXHAN17, BXHAN18, BXHAN15, BXHAN19, BXHAN25, BXHAN21, BXHAN23, BXHAN20, BXHAN22, BXHAN28, BXHAN27, BXHAN24, BXHAN31, BXHAN26, BXHAN30, BXHAN29, BXBREQ0N, BXCPURSTN, BXHDN1, BXHDN0, BXHDN3, BXHDN2, BXHDN5, BXHDN4, BXHDN8, BXHDN6, BXHDN9, BXHDN7, BXHDN14, BXHDN12, BXHDN10, BXHDN15, BXHDN11, BXHDN17, BXHDN13, BXHDN20, BXHDN16, BXHDN18, BXHDN21, BXHDN19, BXHDN23, BXHDN22, BXHDN24, BXHDN25, BXHDN27, BXHDN26, BXHDN30, BXHDN29, BXHDN31, BXHDN28, BXHDN35, BXHDN32, BXHDN33, BXHDN38, BXHDN37, BXHDN34, BXHDN43, BXHDN40, BXHDN36, BXHDN39, BXHDN44, BXHDN45, BXHDN47, BXHDN42, BXHDN41, BXHDN51, BXHDN52, BXHDN49, BXHDN48, BXHDN46, BXHDN59, BXHDN57, BXHDN54, BXHDN53, BXHDN50, BXHDN60, BXHDN56, BXHDN55, BXHDN63, BXHDN61, BXHDN58, BXHDN62, XINTR, XNMI, XIGNEN, XFERRN, XCPUCLK, XCPUSLPN, XSTPCLKN, XA20MN, XINIT, XSMIN, XREQN0, XREQN1, XREQN2, BXAD31, BXAD30, BXAD29, Preliminary V.10 Oct.07,1999 65 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset BXAD28, BXAD27, BXAD26, BXAD25, BXAD24, BXCBEN3, BXAD23, BXAD22, BXAD21, BXAD20, BXAD19, BXAD18, BXAD17, BXAD16, BXCBEN2, BXFRAMEN, BXIRDYN , BXTRDYN, BXDEVSELN, BXPLOCKN, BXSTOPN, BXPAR, BXCBEN1, BXAD15, BXAD14, BXAD13, BXAD12, BXAD11, BXAD10, BXAD9, BXAD8, BXCBEN0, BXAD7, BXAD6, BXAD5, BXAD4, BXAD3, BXAD2, BXAD1, BXAD0, XSDATAO, XACSYNC, XACCLK, BXGPIO0, BXGPIO1, BXGPIO2, XTHERMN
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7
7.1
7.1.1
Register Summary / Description - Core Logic
Device 0, Function 0 ( Host-to-PCI Bridge)
Configuration Space Header Register Name Vendor ID Device ID PCI Command Register Default Value 1039h 0630h 0005h Access Type RO RO RO R/W 06~07h PCI Status Register 0210h RO WC (*) 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10~13h Revision ID Programming Interface Sub-Class Code Base Class Code Cache Line Size Master Latency timer Header Type BIST Graphic Window Base Address 00h 00h 00h 06h 00h FFh 80h 00h 00000000h RO RO RO RO RO R/W RO RO RO R/W 14~33h 34h Reserved Capability Pointer 00h C0h RO RO
Register Address 00~01h 02~03h 04~05h
WC stands for Write Clear. If the register' s access type is WC, that means every write cycle issued to the register can only reset (Write Clear from 1 to 0) the specific bit in the register, but can not set it (write 1 into the corresponding bit). The corresponding bit of the register will be reset when writing " 1" to that bit. For instance, writing value 0100_0000_0000_0000b to the register will clear bit 14 and the other bits keep the same value.
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7.1.2 Registers for Host & DRAM Register Name Host Interface Control 1 Host Interface Control 2 DRAM MISC Control 1 DRAM MISC Control 2 DRAM Timing Control 1 DRAM Timing Control 2 DRAM MISC Control 3 SDRAM/VCM Control Initialization Default Value 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 0000h 00h 00h 00h Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Register Address 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h~5Ah 5Bh 5Ch~5Fh 60h~62h 63h 64h 65h 66h~67h 69h~68h 6Ah 6Bh 6Ch
DRAM Buffer Pre-driver Slew Rating DRAM Buffer Current Rating Strength and
PCI Buffer Strength and Current Rating Reserved DRAM Type Registers of DIMM 0/1/2 DRAM Status Register(Bit-x = DIMM-x ) FBC Control Register DIMMs Switch Control Reserved ACPI I/O Space Base Address Register SMRAM Access Control Self Refresh Command Output Timing Control DRAM Self-Refresh control for Power Management
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7.1.3 Shadow RAM & PCI-Hole Area Register Name Shadow RAM attribute Read/Write Control Reserved Characteristics area of PCI-Hole & Default Value 00000000h 00h 00h 0000h 0000h Access Type R/W RO R/W R/W R/W
Register Address 70h~73h 74h~76h 77h 78h~79h 7Ah~7Bh 7.1.4
Allocation of PCI-Hole area #1 Allocation of PCI-Hole area #2
Hardware-Trap Control Register Name VGA-Bridge Control South-Bridge Control North-Bridge Control Hardware-Trap Hardware-Trap Hardware-Trap Default Value 00h 00h 00h Access Type R/W R/W R/W
Register Address 7Ch 7Dh 7Eh~7Fh
7.1.5
Host Bridge & PCI Arbiter Characteristics Register Name Target Bridge Characteristics to DRAM Default Value 00h Access Type R/W
Register Address 80h
Register Address 81h 82h 83h 84h~85h 86h
Register Name PCI Discard Timer for Delay Transaction PCI Target Characteristics Bridge Bus
Default Value FFh 00h 00h FFFFh FFh
Access Type R/W R/W R/W R/W R/W
CPU to PCI Characteristics PCI Grant Timer CPU Idle Timer for PCI 69
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Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 87h 88h~89h 7.1.6 Host Bridge & Priority Timer PCI Master FFh 0000h R/W R/W
PCI Discard Timer For PCI Hold
Clock Control Register Name SDRCLK/SDWCLK Control SDWCLK Control CPU clock & SDRAM Clock Relationship FBCRCLK/FBCWCLK Control Default Value 2Ah AAh 00h 2Ah Access Type R/W R/W R/W R/W
Register Address 8Ch 8Dh 8Eh 8Fh 7.1.7
GART and Page Table Registers Register Name GART Base Address Default Value 00000000h Access Type R/W RO 94h Graphic Window Control Reserved Page Table Cache Control Page Table Cache Invalidation Control 00h 00h 00h 00h R/W RO R/W R/W
Register Address 90h~93h
95h~96h 97h 98h
7.1.8
Integrated VGA Control Register Name Integrated VGA Control Default Value 00h Access Type R/W
Register Address 9Ch 7.1.9 A.G.P.
Register Address A0h~A3h A4h~A7h
Register Name DRAM Priority Timer Control Register General Purpose Register
Default Value 00000000
Access Type R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset A8h~Abh ACh~AFh C0h~C3h C4h~C7h C8h~CBh General Purpose Register General Purpose Register A.G.P. Register Capability Identify 00200002h 1F000203h 00000000h RO RO R/W
A.G.P. Status Register A.G.P. Command Register
7.2
Device 2, Function 0 (Virtual PCI-to-PCI Bridge)
Register Address 00-01h 02-03h 04-05h Vendor ID Device ID PCI Command Register Register Name Default Value 1039h 0001h 0000h Access Type RO RO RO R/W 06-07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 19h 1Ah 1Bh 1Ch PCI Status Register Revision ID Programming Interface Sub-Class Code Base Class Code Cache Line Size Master Latency timer Header Type BIST Secondary Bus Number Subordinate Bus Number Secondary Master Latency Timer I/O Base 0000h 00h 00h 04h 06h 00h 00h 01h 00h 00h 00h 00h F0h RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W RO 1Dh I/O Limit 00h R/W RO
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1Eh Secondary PCI-PCI Status 0000h R/W RO 20~21h Non-prefetchable Address Non-prefetchable Address Memory Base FFF0h R/W RO Memory Limit 0000h R/W RO FFF0h R/W RO 26~27h Prefetchable Memory Limit Address 0000h R/W RO 28~3Dh 3Eh Reserved PCI to PCI Bridge Control 0000h RW RO
22~23h
24~25h
Prefetchable Memory Base Address
7.3
Register Description -- Core logic
The SIS630 has three programmer visible registers located in the I/O space. These registers are listed in the following table. I/O Space Address 0CF8h 0CFCh Configuration Register Function CONFIG_ADDRESS register (only valid for DWord access) CONFIG_DATA register (only valid if enable bit is set in the CONFIG_ADDRESS register)
7.3.1 7.3.2
Host Bridge Registers (Function 0) Configuration Space Header
Register 00h Vendor ID Default Value: 1039h Access: Read Only The register identifies the manufacturer of the device. SiS is allocated as 1039h by PCI SIG. Bit 15:0 Access RO Description Vendor Identification Number
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 02h Device ID Default Value: 0630h Access: Read Only The device identifier is allocated as 0630h by Silicon Integrated Systems Corp. Bit 15:0 Access RO Description Device Identification Number
Register 04h Command Default Value: 0005h Access: Read/Write, Read Only The Command register provides coarse control over a device' s ability to generate and respond to PCI cycles. Bit 15:3 2 Access RO RO Description Reserved Bus Master Default value is 1. That means you cannot disable bus master function of the host bridge. Memory Space The bit controls the response to memory space accesses. When the bit is disabled, the host bridge ignores all access from PCI masters. 0: Disable 1: Enable 0 RO I/O Space Default value is 1. The host bridge only respond to the addresses 0CF8h and 0CFCh in the I/O space and the I/O transaction must be generated by the host bridge itself.
1
R/W
Register 06h Status Default Value: 0210h Access: Read Only, Write Clear The Status register is used to record status information for PCI bus related events. Reads to this register behave normally. Writes are slightly different in that? each bit in this register can only be reset(Write Clear from 1 to 0), but not set. The corresponding bit of the register will be reset when writing " 1" to that bit. For instance, to write value 0100_0000_0000_0000b to the register will clear bit 14 and not affect any other bits. Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 15:14 RO Reserved This bit is always 0, SIS630 does not support parity checking on the PCI bus. Received Master Abort SIS630 sets this bit whenever its transaction is terminated with master abort. Writing a 1 to it clears this bit. Received Target Abort. SIS630 sets this bit whenever it terminates a transaction with target abort. Writing a 1 to it clears this bit. Reserved DEVSEL# Timing DEVT. These two bits define the timing to assert DEVSEL#. SIS630 always asserts DEVSEL# within two clocks after the assertion of FRAME#. Reserved CAP_LIST The value of " 1" for this bit specifies SIS630' s configuration space implements a list of capabilities. Reserved
13
WC
12
WC
11 10:9
RO RO
8:5 4
RO RO
3:0
RO
Register 08h Revision ID Default Value: 01h Access: Read Only The Revision ID is 01h for A1 Revision. Bit 7:0 Access RO Description Revision Identification Number
Register 09h Programming Interface Default Value: 00h Access: Read Only The default value is 00h since no specific register-level programming interface is provided. Bit 7:0 Access RO Programming Interface Description
Register 0Ah Sub Class Code Default Value: 00h Preliminary V.10 Oct.07,1999 74 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Access: Read Only The Sub Class Code is 00h for host bridge. Bit 7:0 Access RO Description Sub Class Code
Register 0Bh Base Class Code Default Value: 06h Access: Read Only The value of 06h in this field identifies a bridge device. Bit 7:0 Access RO Description Base Class Code
Register 0Ch Cache Line Size Default Value: 00h Access: Read Only The value of this register is always 00h since the host bridge won' t generate the Memory Write and Invalidate command. Bit 7:0 Access RO Cache Line Size Description
Register 0Dh Master Latency Timer (MLT) Default Value: FFh Access: Read/Write The MLT is used in conjunction with PGT (Register84h) and CIT (Register 86h) to provide a fair and efficient system arbitration mechanism. The value of MLT guarantees the minimum system bandwidth for CPU when CPU and PCI masters are all craving for system resources (system memory or PCI bus). Bit 7:0 Access R/W Description Initial Value for Master Latency Timer
Register 0Eh Header Type Default Value: 80h Access: Read Only The value of 80h implies that SIS630 is a multiple function device. Bit 7:0 Access RO Header Type Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 0Fh BIST Default Value: 00h Access: Read Only The value is 00h since we don' t support Build-in Self Test. Bit 7:0 Access RO Description BIST
Register 10h Graphic Window Base Address (GWBA) Default Value: 00000000h Access: Read/Write, Read Only The register defines the starting address of the graphic window for A.G.P. The Graphic Window Control Register (Register 94h) controls accessibility and effectiveness of this register. Bit 31:22 Access R/W RO Description Define A[31:22] of Graphic window base address The accessibility of bits[31:22] are controlled by graphic window size(Bits[6:4], Register 94h). Bit31 R/W R/W R/W R/W R/W R/W R/W 21:0 RO Bit30 R/W R/W R/W R/W R/W R/W R/W Bit29 R/W R/W R/W R/W R/W R/W R/W Bit28 R/W R/W R/W R/W R/W R/W R/W Bit27 R/W R/W R/W R/W R/W R/W 0 Bit26 R/W R/W R/W R/W R/W 0 0 Bit25 R/W R/W R/W R/W 0 0 0 Bit24 Bit23 Bit22 Size R/W R/W R/W R/W R/W 0 R/W 0 0 16M 0 0 0 32M 0 0 0 64M 0 0 0 128M 0 0 0 256M
Reserved and read as 000000h
Register 34h Capability Pointer (CAPPTR) Default Value: C0h Access: Read Only The value of C0h indicates that the A.G.P. standard register block is started from Register C0h. Bit 7:0 Access RO Description Capability Pointer Pointer to the Start of A.G.P. standard register block.
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7.3.3 Host Control Registers
Register 50h Host Bus Interface Control I Default Value 00h Access Read/Write This register defines the functions supported by the Host interface. Bit 7 Access R/W Description Host Defer Function When this bit is enabled, host block will defer CPU to PCI nonpost cycle and issue a Defer Reply cycle later to increase host bus usage efficiency. 0: Disable 1: Enable 6:5 4 R/W R/W Reserved Host Read/Write Reorder When this bit is enabled, DRAM read cycle may exceed DRAM write cycle in DRAM side for increasing performance. 0: Disable 1: Enable 3 R/W CPU & PCI Masters Concurrently Access Memory Function When this bit is enabled, CPU access memory cycles and PCI masters access memory cycles can be concurrently issued onto host bus and PCI bus, respectively, and then the memory access cycles will be rearranged by SIS630 to memory sequentially. In this case, the utilization of the buses will be optimized. When this bit is disabled, either CPU or PCI masters starts memory access cycle will block the other one' s cycle until the current cycle is finished. 0: Disable 1: Enable
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 2 R/W CPU & PCI Masters Concurrently Access PCI Bus Function When this bit is enabled, CPU access PCI bus cycle and PCI masters access memory cycles can be concurrently issued onto host bus and PCI bus, respectively. By doing this, these cycles will be forwarded to PCI bus and memory bus at the same time. This bit is valid only bit 3 is set. When this bit is disabled, either one of these two kinds of cycles will block the other until the current cycle is finished. 0: Disable 1: Enable 1 R/W CPU Pipeline Function When this bit is 0, only one pending cycle is allowed at one time. When this bit is 1, there might be more than two pending cycles at one time depends on the CPU behaviour. 0: no pipeline 1: pipeline enable 0 R/W Reserved
Register 51h Host Bus Interface Control II Default Value 00h Access Read/Write This register defines the functions supported by the Host interface. Bit 7:2 1 Access R/W R/W Description Reserved Host-to-PCI Cycle Timing Control When set to 1, the Host-to-PCI bridge will start the transaction of Host-to-PCI cycle once the cycle appears on the host bus. When set to 0, the start of the Host-to-PCI translation will be delayed by one CPU clock. 0: Delay 1 CPU clock 1: Without Delay 0 7.3.4 R/W Reserved
DRAM Control Registers DRAM MISC Control 1 00h 78 Silicon Integrated Systems Corporation
Register 52h Default Value
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Access Read/Write The register defines timing for Refresh cycles. Bit 7:6 Access R/W Description DRAM Refresh Queue Depth These two bits control the depth of refresh queue. To minimize the performance penalty caused by refresh cycles, the concept of refresh queue is introduced. Refresh request is arbitrated with other DRAM request, if a refresh request does not get served, it enters the refresh queue. The priority of refresh request is promoted to highest when the refresh queue is full.
Bits[7:6] Depth
00 01 10 11 5:4 R/W
0 4 8 12
DRAM Refresh Period Control These two bits are used to determine how often will the refresh request occur. It is timed with a counter based on PCI clock. 00: 15.6us 01: 7.8us 10: 3.9us 11: Reserved
3
R/W
Starting Point Control for Ahead Refresh This bit controls how long should the DRAM arbiter wait before issuing the first ahead refresh request when the bus is idle. For further reducing the performance penalty caused by refresh cycles, SIS630 provides ahead refresh function. When the bus is idle, if no DRAM request is issued during a specific time, the DRAM arbiter will issue refresh request to utilize the bus. In the following 10T, if no other request is issued, another ahead refresh request will be issued. And so on. The maximum number of ahead refresh cycles can be issued is 32. 0: 10T 1: 40T
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 2 R/W Ahead Refresh Function Control This bit enables the ahead refresh function. 0: Disable 1: Enable 1 R/W DRAM Refresh Test Mode This bit is used to test internal refresh circuit. In test mode, refresh request will be issued per 0.5us. For normal operation, it must be programmed with 0. 0: Normal Mode 1: Test Mode 0 R/W Refresh Cycle Enable When disabled, the normal refresh cycle issued from SIS630 will be prohibited. This function is used by BIOS to perform SDRAM / VCM initialization, during which period SDRAM / VCM can still be refreshed by programming register 57h bit 5. For normal operation, this bit should be programmed with 1. 0: Disable 1: Enable Register 53h DRAM MISC Control 2 Default Value 00h Access Read/Write This register controls the queue depth used in DRAM controller. Bit 7:6 5 Access R/W R/W Description
Reserved
CPU-to-MEM Cycle Pipelined Control 0: Normal 1: Slower
4
R/W
Host / AGP Command Queue Depth This bit defines the depth of command queue in DRAM arbiter.
Bit[4] Depth
0 1
2 1
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3:1 R/W Foreground Queue Depth Bits[3:1] defines the depth of foreground queue in memory controller.
Bits[3:1] Depth
000 001 010 011 100 101
6 5 4 3 2 1
Others : Reserved 0 R/W Background Queue Depth Bit 0 defines the depth of background queue in memory controller. 0: 2-level 1: 1-level Register 54h DRAM Timing Control 1 Default Value 00h Access Read/Write This register controls the timing for SDRAM. Bit 7:6 Access R/W Description SDRAM RAS Active Time (tRAS) Bits[7:6] defines SDRAM ACT to PRE command period
Bits[7:6] Pulse Width
00 01 10 11
6T 7T 5T 4T
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5:4 R/W SDRAM RAS# Precharge Time (tRP) Bits[5:4] defines SDRAM PRE to ACT command period
Bits[5:4] Pulse width
00 01 10 11 3:2 R/W
3T 2T 4T Reserved
SDRAM RAS to CAS Delay (tRCD) Bits[3:2] defines SDRAM ACT to Read/Write command period
Bits[3:2] Pulse Width
00 01 10 11 1 R/W
3T 2T 4T Reserved
SDRAM Refresh Cycle Time (tRC) Bit 1 defines SDRAM REF to REF/ACT command period 0: tRC = tRAS + tRP 1: tRC = tRAS + tRP + 1T
0
R/W
DRAM Refresh Command to Different Rank Control When this bit is enabled, refresh commands to different DRAM ranks initiated by SIS630 will be staggered one clock apart, such that simultaneous-switching noise can be reduced. When disabled, SIS630 will issue refresh commands to different DRAM ranks simultaneously. 0: Simultaneous 1: Staggered one clock apart
Register 55h DRAM Timing Control 2 Default Value 00h Access Read/Write This register controls the timing for VCM and SDRAM. Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7 R/W Invalidate VCM Table When this bit is enabled, VCM table will be invalidated. BIOS should disable this bit after it was enabled. This bit is used during DRAM initialization sequence. 0: Disable 1: Enable 6 R/W VCM ACT to Prefetch Command Delay Time (tAPD) This bit defines VCM ACT to Prefetch command period. 0: 2T 1: 3T 5:4 R/W VCM ACT to ACT/REF Delay (tRC) These two bits define VCM ACT to ACT/REF command period. 00: 10T 01: 9T 10: 8T 11: Reserved 3 R/W VCM REF to REF/ACT Delay (tRCF) This bit defines VCM REF to REF/ACT command period. 0: 10T 1: 9T 2 R/W Write Recovery Time (tWR) This bit defines the Data-in to PRE command period, tWR. 0: 1T 1: 2T 1 R/W SDRAM ACT to ACT Delay (tRRD) Bit 1 defines SDRAM ACT(one) to ACT(another) command period. 0: 2T 1: 3T
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 R/W MDOE# Enable Control When enabled, SIS630 can drive output data to DRAM. BIOS should turn on this bit before SDRAM / VCM initialization sequence. 0: Disable 1: Enable Register 56h DRAM MISC Control 3 Default Value 00h Access Read/Write Bit 7 Access R/W Description Memory Command Output Timing Control This bit is used to control the timing to drive memory command onto memory bus. When heavy loading memory is used, signal propagation delay may be more than 1 clock. In this case, enabling this bit will force all memory command delay 1 clock except self refresh command and the reference clocks are adjustable clocks defined in register 8Ch and 8Dh. 0: Normal 1: Delay 1T 6 R/W Lead-off Time Control for DRAM Background Command When set to 0, background commands are issued 1 clock behind memory address (MA) been? issued. When set to 1, background command and MA are issued at the same time. 0: Delay 1T 1: Normal 5 R/W Lead-off Time Control for DRAM Read/Write Cycles When set to 0, memory read/write command is issued 1 clock behind memory address (MA) ?been issued. When set to 1, read/write command and MA are issued at the same time. 0: Delay 1T 1: Normal 4 R/W VCM ACT to RSTA Command Delay Control When set to 1, the ACT to RSTA timing constraint will be delayed one more clock. 0: Normal 1: Delay 1 Clock
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3 2 R/W R/W
Reserved
One Page/Channel Control When set to 1, only one SDRAM page or one VCM channel will be activated (opened) during DRAM access. 0: Normal 1: Only One Page/Channel
1
R/W
Foreground and Background Command Out-of-Order Control When set to 0, background commands may go ahead than foreground commands for increasing DRAM utilization. When set to 1, background and foreground commands operate in sequence. 0: Out-of-Order 1: In-Order Read / Write Combine Function Control When set to 0, contiguous single R/W and double read cycles may be combined into a burst cycle. When set to 1, this function is disabled. 0: Enable 1: Disable
0
R/W
Register 57h SDRAM/VCM Initialization Control Default Value 00h Access Read/Write This register controls SDRAM / VCM initialization process and timing. Bit 7 Access R/W Description Precharge Command When this bit is set, SIS630 will issue the precharge command to SDRAM / VCM. This bit is automatically cleared after the precharge command is completed. 0: Disable 1: Enable
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 6 R/W Mode Register Set Command When this bit is set, SIS630 will issue mode register setting command to SDRAM or SCLR Command to VCM. This bit is automatically cleared after the mode register setting command is completed. 0: Disable 1: Enable 5 R/W Refresh Command When this bit is set, SIS630 will issue refresh command to SDRAM / VCM. This bit is automatically cleared after the refresh command is completed. 0: Disable 1: Enable 4 R/W VCM Set Channel Control Register Command When this bit is set, SIS630 will issue SCCR command to VCM. This bit is automatically cleared after the refresh command is completed. 0: Disable 1: Enable 3 2 R/W R/W
Reserved
Do No Operation Command Control When this bit is set to 1, precharge command set by R57b7 will be turned into No Operation (NOP) command. When this bit is set to 0, precharge command operates normally. 0: Normal 1: Precharge command turn into NOP Command
1
R/W
VCM Command Truth Table Select This bit selects the version of VCM command truth table that will be used in memory controller. 0: NEC version 1: JEDEC version
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 R/W SDRAM /VCM CAS# Latency (CL) Setting This bit contains the information for SDRAM initialization procedure. 0: 2T 1: 3T Register 58h Memory Buffer Pre-driver Slew Rating Default Value 00h Access Read/Write This register controls the pre-driver slew rate of DRAM related signals. Bit 7 Access R/W Description VDQM[7:0] / VMD[63:0] Pre-driver Slew Rating 0: Slow 1: Fast 6 R/W VCS# / VBA1 / VMA[11:10] Pre-driver Slew Rating 0: Slow 1: Fast 5 R/W CKE Pre-driver Slew Rating 0: Slow 1: Fast 4 R/W CSB[5:0]# Pre-driver Slew Rating 0: Slow 1: Fast 3 R/W CSA[5:0]# Pre-driver Slew Rating 0: Slow 1: Fast 2 R/W DQM[7:0] Pre-driver Slew Rating 0: Slow 1: Fast 1 R/W MD[63:0] Pre-driver Slew Rating 0: Slow 1: Fast
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 R/W SRAS# / SCAS# / WE# / MA[14:0] Pre-driver Slew Rating 0: Slow 1: Fast Register 59h Memory Buffer Strength and Current Rating Default Value 00h Access Read/Write This register controls the buffer strength of DRAM related signals. Bit 7:6 Access R/W Description VDQM[7:0] / VMD[63:0] Driving Rating 00: Weak 01: Normal 10: Strong 11: Strongest 5:4 R/W VCS# / VBA1 / VMA[11:10] Driving Rating 00: Weak 01: Normal 10: Strong 11: Strongest 3:2 R/W CKE Driving Rating 00: Weak 01: Normal 10: Strong 11: Strongest 1:0 R/W CSB[5:0]# Driving Rating 00: Weak 01: Normal 10: Strong 11: Strongest Register 5Ah Memory Buffer Strength and Current Rating Default Value 00h Access Read/Write This register controls the buffer strength of DRAM related signals. Preliminary V.10 Oct.07,1999 88 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bit 7:6 Access R/W Description CSA[5:0]# Driving Rating 00: Weak 01: Normal 10: Strong 11: Strongest 5:4 R/W DQM[7:0] Driving Rating 00: Weak 01: Normal 10: Strong 11: Strongest 3:2 R/W MD[63:0] Driving Rating 00: Weak 01: Normal 10: Strong 11: Strongest 1:0 R/W SRAS# / SCAS# / WE# / MA[14:0] Driving Rating 00: Weak 01: Normal 10: Strong 11: Strongest Register 5Bh PCI Buffer Strength and Current Rating Default Value 00h Access Read/Write This register controls the buffer strength of PCI bus related signals. Bit 7:2 1 Access R/W R/W Reserved AD[31:0] Current Rating This bit controls the buffer strength of AD[31:0] on PCI bus. 0: Weak 1: Strong Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 R/W PCI Control Signals Current Rating This bit controls the buffer strength of FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, PAR, C/BE[3:0]# and GNT[2:0]#. 0: Weak 1: Strong Register 60h/61h/62h for DIMM x=0..2 Default Value 00h Access Read/Write Bit 7 Access R/W
DRAM Mode Selection
DRAM Type Registers
Description 0: SDRAM 1: VCM
6 5
R/W R/W
Reserved DRAM Configuration Selection 0: Single side 1: Double side
4 3:0
R/W R/W
Reserved DRAM Type Selection SDRAM (NBAxNRAxNCA) 0000: 1x11x8(8M) 0010: 2x12x8(32M) 0100: 1x11x9(16M) 0110: 2x12x9(64M) 1000: 1x11x10(32M) 1010: 2x12x10(128M) 1100: 2x11x8(16M) 1110: 2x12x11(256M)
VCM (NBAxNRAxNCAxNSA)
0001: 1x13x8(32M) 0011: 2x13x8(64M) 0101: 1x13x9(64M) 0111: 2x13x9(128M) 1001: 1x13x10(128M) 1011: 2x13x10(256M) 1101: 1x13x11(256M) 1111: 2x13x11(512M)
0000: 1x13x6x2(32M) 0010: 1x13x8x2(128M)
0001: 1x13x7x2(64M) Others : Reserved
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 63h DRAM Status Register (bit-x =DIMM-x) Default Value 00h Access Read/Write Bit 7 Access R/W Description Shared Memory Control 0: Disable 1: Enable 6:4 R/W Shared Memory Size on DIMM0
Bits[6:4] mode) Size (Total Share Memory size for 128-bit
000 001 010 011 100 101
2M 4M 8M 16M 32M 64M
4M 8M 16M 32M 64M Not Supported
Others : Reserved 3 2 R/W R/W Reserved DRAM DIMM2 Status 0: Absent 1: Installed 1 R/W DRAM DIMM1 Status 0: Absent 1: Installed 0 R/W DRAM DIMM0 Status 0: Absent 1: Installed Register 64h Frame Buffer Cache (FBC) Control Register Default Value 00h Access Read/Write Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7 R/W FBC Sizing Control This bit is used by BIOS during FBC initialization sequence. Before FBC sizing sequence, this bit is set to 1. After FBC sizing sequence is finished, BIOS should set this bit to 0. 0: Disable 1: Enable 6 R/W Force Two Banks Control After initialization sequence, if FBC is populated and its internal bank number is different from DIMM0, then this bit should be set to 1. 0: Disable 1: Enable 5 R/W Graphics Memory Data Bus Width Control This bit controls graphics memory data bus width. If FBC is not populated, it should be programmed with 0. If FBC is populated, it can be programmed with 1. 0: 64-bits 1: 128-bits 4 R/W FBC Status 0: Absent 1: Installed 3:0 R/W FBC Type Selection FBC mode is the same as DIMM0. Bits[3:0] defines FBC type. SDRAM (NBAxNRAxNCA) 0000: 1x9x8(2M) 0010: 1x11x8(8M) 0100: 1x11x9(16M) 0110: 2x11x8(16M) Others : Reserved
VCM (NBAxNRAxNCAxNSA)
0001: 1x10x8(4M) 0011: 2x12x8(32M) 0101: 1x11x10(32M) 0111: 1x12x8(16M)
0000: 1x13x6x2(32M) Others : Reserved
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 65h DIMM Location for SMA Default Value: 00h Access: Read/Write Bit 7:2 1:0 Access R/W R/W Reserved DIMM Location for SMA The Share memory used by GUI can be located at any bank which is determined by BIOS during DRAM Detection Sequence. Please refer to BIOS Programming Guide for detail. Description
Power Management Register 69~68h ACPI I/O Space Base Address Register Default Value 0000h Access Read/Write Bit 15:5 Access R/W Description A[15:5] for ACPI I/O Space base Address This register provides A[15:5] for the start address of the ACPI I/O space. Reserved Validity Bit If this bit is set to 1, the base address contained in Bit[15:5]is in valid. Otherwise the base address defined in Bit[15:5] is ignored. 0: Invalid 1: Valid Register 6Ah SMRAM Access Control Register Default Value 00h Access Read/Write Bit Access Description
4:1 0
R/W R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:5 R/W SMRAM Area Re-mapping Control This field controls how the address in the host bus is mapped to the system memory address when the SMRAM access control bit is enabled or CPU is in the system management mode.
Bits[7:5] Host Address System Memory Address
000 010 100 110 001 111 4 R/W
E0000h~E7FFFh E0000h~E7FFFh E0000h~E7FFFh A0000h~AFFFFh B0000h~BFFFFh A0000h~BFFFFh
E0000h~E7FFFh (32K) A0000h~A7FFFh (32K) B0000h~B7FFFh (32K) A0000h~AFFFFh (64K) B0000h~BFFFFh (64K) A0000h~BFFFFh (128K)
SMRAM Access Control When this bit is enabled, SMRAM area can be used even when SMIACT# is not asserted, this function is mainly used for SMRAM initialization by BIOS. When this bit is disabled, SMRAM area can only be accessed during the SMI handler. 0: Disable 1: Enable
3:2 1:0
R/W R/W
Reserved For Internal Testing Use
Register 6Bh Self Refresh Command Output Timing Control Default Value 00h Access Read/Write Bit 7:1 0 Access R/W R/W Reserved Self Refresh Command Output Timing Control When this bit is enabled, self refresh command will be delayed 1 clock. 0: Normal 1: Delay 1T Register 6Ch DRAM Self-Refresh Control for Power Management Default Value 00h Access Read/Write Preliminary V.10 Oct.07,1999 94 Silicon Integrated Systems Corporation Description
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset This register controls the ACPI sleep states supported by SIS630. Bit 7 Access R/W Description ACPI S3 States Support 0: Disable 1: Enable 6 R/W ACPI S2 States Support 0: Disable 1: Enable 5 R/W CKE Output Enable Control When enabled, SIS630 drives CKE. When disabled, SIS630 floats its CKE output. 0: Disable 1: Enable 4 R/W CKE Selection This bit is controlled by BIOS during power management mode, and is valid only when CKE Output Enable Control bit was enabled. When set to 1, SIS630 always drives CKE to low. When set to 0, SIS630 drives CKE to low only when it enters self-refresh mode (S2 or S3 state and stop grant cycle issued). 0: Normal Mode 1: Force Low 3:1 R/W Early CKE Delay Adjustment These bits control the timing for CKE. Various delay options are provided to ensure that CKE can meet SDRAM setup time and hold time specification when CKE is driven out.
Bit[3:1] Descriptions
000 001 010 011 100 101 110 111
Delay 1ns Delay 2ns Delay 3ns Delay 4ns Delay 5ns Delay 6ns Delay 7ns Delay 8ns
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 R/W Early CKE Delay 1T Control When this bit is enabled, CKE is driven out from flip-flop. It is used when system operates under low frequency and CKE delay adjustment method defined in Bits[3:1] can not meet setup time and hold time requirement. 0: Normal 1: Delay 1T 7.3.5 Shadow RAM Area
Register 70h Shadow RAM Read Attribute Control This register defines the read accessibility of each shadow RAM region Bit 15 Access R/W Description Shadow RAM Enable for PCI Master Access When this bit is enabled, accesses from PCI masters toward shadow RAM area is allowed. 0: Disable 1: Enable 14:13 12 R/W R/W Reserved Read Accessibility of Shadow Region F0000h~FFFFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus. Read Accessibility of Shadow Region EC000h~EFFFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus. Read Accessibility of Shadow Region E8000h~EBFFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus. Read Accessibility of Shadow Region E4000h~E7FFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus.
11
R/W
10
R/W
9
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 8 R/W Read Accessibility of Shadow Region E0000h~E3FFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus. Read Accessibility of Shadow Region DC000h~DFFFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus. Read Accessibility of Shadow Region D8000h~DBFFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus. Read Accessibility of Shadow Region D4000h~D7FFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus. Read Accessibility of Shadow Region D0000h~D3FFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus. Read Accessibility of Shadow Region CC000h~CFFFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus. Read Accessibility of Shadow Region C8000h~CBFFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus. Read Accessibility of Shadow Region C4000h~C7FFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus. Read Accessibility of Shadow Region C0000h~C3FFFh When this bit is set to 1, the data of the read accesses toward the corresponding region are returned from system memory. When this bit is set to 0, the data are returned from PCI bus.
7
R/W
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
Register 72h
Shadow RAM Write Attribute Control 97 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bit 15:13 12 Access R/W R/W Description Reserved Write Accessibility of Shadow Region F0000h~FFFFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus. Write Accessibility of Shadow Region EC000h~EFFFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus. Write Accessibility of Shadow Region E8000h~EBFFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus. Write Accessibility of Shadow Region E4000h~E7FFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus. Write Accessibility of Shadow Region E0000h~E3FFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus. Write Accessibility of Shadow Region DC000h~DFFFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus. Write Accessibility of Shadow Region D8000h~DBFFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus. Write Accessibility of Shadow Region D4000h~D7FFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus. Write Accessibility of Shadow Region D0000h~D3FFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus. 98 Silicon Integrated Systems Corporation
11
R/W
10
R/W
9
R/W
8
R/W
7
R/W
6
R/W
5
R/W
4
R/W
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3 R/W Write Accessibility of Shadow Region CC000h~CFFFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus. Write Accessibility of Shadow Region C8000h~CBFFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus. Write Accessibility of Shadow Region C4000h~C7FFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus. Write Accessibility of Shadow Region C0000h~C3FFFh When this bit is set to 1, the data of the write accesses toward the corresponding region are forwarded to system memory. When this bit is set to 0, the data are forwarded from PCI bus.
2
R/W
1
R/W
0
R/W
7.3.6
PCI Hole Area
Register 77h Characteristics of PCI-Hole Area Default Value 00h Access Read/Write This register controls the PCI Hole area support. When a PCI hole area is enabled, a cycle with the address located within the PCI hole area will be forwarded to PCI bus. Bit 7:3 2 Access R/W R/W Description Reserved PCI-Hole Area I Enable 0: Disable 1: Enable 1 0 R/W R/W Reserved PCI-Hole Area II Enable 0: Disable 1: Enable Register 78h Allocation of PCI-Hole Area #1 Default Value 0000h Access Read/Write Preliminary V.10 Oct.07,1999 99 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 78h and 79h define the size and the base address of the first PCI-Hole area. Bit 15:13 Access R/W Description Size of PCI-Hole Area I (within 512 Mbytes)
Bits[15:13] Size
000 001 010 011 100 101 110 111 12:0 R/W
64KB 128KB 256KB 512KB 1MB 2MB 4MB 8MB
Base Address of PCI-Hole Area I This field specifies A[28:16] for the base address of the PCIHole area.
Register 7Ah Allocation of PCI-Hole Area #2 Default Value 00h Access Read/Write Bit 15:13 Access R/W
Bits[15:13] Size
Description Size of PCI-Hole Area II (within 512 Mbytes) 000 001 010 011 100 101 110 111 64KB 128KB 256KB 512KB 1MB 2MB 4MB 8MB
12:0
R/W
Base Address of PCI-Hole Area II This field specifies A[28:16] for the base address of the PCIHole area.
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7.3.7 Hardware-Trap Control
Register 7Ch VGA-Bridge Hardware-Trap Control Default Value 00h Access Read/Write 7:0 R/W VGA-Bridge Hardware-Trap Control These bits control VGA-Bridge Hardware-Trap status. In read mode, these bits store the Hardware-Trap result; in write mode, these bits specify the Hardware-Trap value. Bit[7:0]: MD[39:32] Register 7Dh South-Bridge Hardware-Trap Control Default Value 00h Access Read/Write 7:0 R/W South-Bridge Hardware-Trap Control These bits control South-Bridge Hardware-Trap status. In read mode, these bits store the Hardware-Trap result; in write mode, these bits specify the Hardware-Trap value. Bit[7:0]: MD[47:40] Register 7Eh North-Bridge Hardware-Trap Control I Default Value 00h Access Read/Write 7:0 R/W North-Bridge Hardware-Trap Control These bits control North-Bridge Hardware-Trap status. In read mode, these bits store the Hardware-Trap result; in write mode, these bits specify the Hardware-Trap value. Bit[7:0]: MD[55:48] Register 7Fh North-Bridge Hardware-Trap Control II Default Value 00h Access Read/Write 7:0 R/W North-Bridge Hardware-Trap Control These bits control North-Bridge Hardware-Trap status. In read mode, these bits store the Hardware-Trap result; in write mode, these bits specify the Hardware-Trap value. Bit[7:0]: MD[63:56]
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 80h Target Bridge to DRAM Characteristics Default Value 00h Access Read/Write This register controls the characteristics for PCI target bridge to access DRAM. Bit 7:5 Access R/W Description Address Boundary Alignment for PCI Bursting This field controls the alignment of address boundaries. For SIS630, a master-generated PCI burst cycle can never ?across any address boundary defined by this field. If a cycle is trying to ?across an address boundary for a memory burst transaction, SIS630 will terminate this transaction with disconnection immediately.
Bits[7:5] Boundary Alignment
000 001 010 011 100 Others 4:1 0 R/W R/W Reserved
256 Bytes 512 Bytes 1K Bytes 2K Bytes 4K Bytes Reserved
PCI Master Delay Transaction Enable This bit controls whether or not SIS630 enable PCI masters delay transactions. PCI Discard Time for Delay Transaction (Register 81h) can only take effect when this bit is enabled. 0: Disable 1: Enable
Register 81 PCI Discard Timer for Delay Transaction Default Value: FFh Access: Read/Write The timer is used to prevent PCI master from seizing PCI bus too long when PCI master starts a delay transaction. When the timer expires, SIS630 will flush CPU-to-PCI FIFO to abort the current PCI transaction. Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:0 R/W PCI Discard Timer for Delay transaction This timer is used to guarantee PCI read transaction is completed in the timer. If not, the read data is discarded. Unit: CPU clock Register 82h Target Bridge Characteristics Default Value 00h Access Read/Write This register controls the characteristics for PCI Target Bridge. Bit 7 6 Access R/W R/W Reserved PCI Master Write Cycle Following Read Cycle Pipeline Control When this bit is disabled, any PCI master write cycle won' t be issued to the addressed target until PCI read FIFO is empty. In this case, there are wait states asserted between the target executes two consecutive PCI read cycle and PCI write cycle. When this bit is enabled, PCI write cycles will be generated to the addressed target right after the previous PCI read cycle, independent of the PCI read FIFO status. 0: Disable 1: Enable 5 R/W PCI Memory Read Line or Memory Read Multiple Command Prefetch Enable This bit controls whether or not SIS630 prefetch data for Memory Read Line or Memory Read Multiple command. 0: Disable 1: Enable 4 R/W PCI Memory Read Command Prefetch Enable This bit controls whether or not SIS630 prefetch data for Memory Read command. 0: Disable 1: Enable Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3:2 R/W Initial Latency Control This field controls the target initial latency of the target bridge. If SIS630 is unable to assert TRDY# for a transaction within the target initial latency defined by this field, SIS630 asserts STOP# to retry this cycle. 00: Disable 01: 16 PCI Clocks 10: 24 PCI Clocks 11: 32 PCI Clocks 1 R/W Subsequent Latency Control When this bit is enabled, SIS630 terminates a transaction with STOP# if it fails to assert TRDY# for the subsequent block within 8 clocks. 0: Disable 1: Enable 0 R/W PCI Memory Read Multiple Lines Control This bit is only valid whenever PCI master memory read prefetch function is enabled, which function is controlled by Register 82h bits[5:4]. When this bit is 0, one more pending memory read prefetch cycle will be issued by SIS630 for PCI masters; When this bit is 1, two more pending memory read prefetch cycles can be generated. 0: 1 more pending cycle 1: 2 more pending cycles Register 83h CPU to PCI Characteristics and Arbitration Option Default Value 00h Access Read/Write Bit 7 Access R/W Description Tri-state Control of Secondary IDE Channel 0: Enable Secondary IDE Channel Signals (default) 1: Tri-state Secondary IDE Channel Signals 6 R/W Tri-state Control of Primary IDE Channel 0: Enable Primary IDE Channel Signals (default) 1: Tri-state Primary IDE Channel Signals
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5 R/W PGT & PDT Test Mode 0: Disable 1: Enable 4 R/W Lock Control When this bit is enabled, SIS630 converts a 64-bit memory cycle on host bus to 2 locked 32-bit memory read cycles on PCI bus. SIS630 also issues locked cycles on PCI bus on behalf of CPU. When this bit is disabled, SIS630 never asserts Lock# on PCI bus. 0: Disable 1: Enable 3 R/W CPU Involved Arbitration on PCI PGT (Register 84h), CIT (Register 86h) and MLT (Register 0Dh) can only take effect when this bit is enabled. When this bit is enabled, SIS630 doesn' t block CPU from operation longer than the period defined by PGT to serve PCI masters, and minimum access time for CPU is guaranteed by MLT. 0: Disable 1: Enable 2 R/W Non-Post Cycle Retry Behavior Control When this bit is 1, if retry occurs from any kind of CPU to PCI non-post cycles, SIS630 won' t back off CPU immediately, but tries to issue one more retry cycle to try to complete the cycle successfully on PCI bus. When this bit is 0, retry from any non-post CPU to PCI cycle results in CPU back off. 1: Try one more time 0: Backoff CPU 1 R/W Memory Burst Control This bit controls whether or not the host bridge generates memory burst cycles. 0: Disable 1: Enable
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 R/W Memory Post Write Control When this bit is enabled, all CPU to PCI memory write cycles are posted. 0: Disable 1: Enable Register 84 PCI Grant Timer Default Value: FFFFh Access: Read/Write The timer is used to prevent PCI masters from seizing the PCI bus too long. When the timer expires, PCI arbiter forces the master that is currently occupying PCI bus to relinquish PCI bus by removing its grant. Bit 15:0 Access R/W Description Initial Value of PCI Grant Timer The setting of this register should consider the overall system configuration and the value of MLT(Register 1Dh). For a system that has many PCI master devices, the value should be higher. For a system with fewer master devices, the value should be smaller. Unit: PCI clock Register 86h CPU Idle Timer Default Value: FFh Access: Read/Write Bit 7:0 Access R/W Description Initial Value of CPU Idle Timer
Register 87h Host Bridge & PCI Master Priority Timer Default Value: FFh Access: Read/Write SIS630 supports the concurrency between CPU to PCI accesses and PCI to system memory accesses. During the period of concurrency, this timer is used to balance the PCI bandwidth between CPU and PCI masters. Bit 7:0 Access R/W Description Host Bridge & PCI Master Priority Timer
Register 88h PCI Discard Timer for PCI Hold Default Value: 0000h Preliminary V.10 Oct.07,1999 106 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Access: Bit 15:0 Read/Write Access R/W Description PCI Discard Timer for PCI Hold This timer is used to keep PCI hold when PCI read is retried due to the CPU-to-PCI post write FIFO is not empty. Unit: CPU clock CPU/PCI Clocks DLL Control Registers Register 8Ch SDRCLK/SDWCLK Control Register Default Value: 2Ah Access: Read/Write To improve the setup time of MD for read/write DRAM, SIS630 introduces two clocks, SDRCLK and SDWCLK, that have some phase differences from SDCLK, which is the clock that applies to SDRAM. Adjusting these two clocks lets the target to have more setup time budget. However, it decreases the hold time. Bit 7:4 Access R/W Description SDRCLK Control This field controls the phase of SDRCLK that lags behind SDCLK.
Bit[7:4] Descriptions Bit[7:4] Descriptions
1111 1110 1101 1100 1011 1010 1001 1000
+6.5ns +6.0ns +5.5ns +5.0ns +4.5ns +4.0ns +3.5ns +3.0ns
0111 0110 0101 0100 0011 0010 0001 0000
+2.5ns +2.0ns +1.5ns +1.0ns +0.5ns +0.0ns (default) -0.5ns -1.0ns
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3:0 R/W SDWCLK Control for CS# This field controls the phase of SDWCLK used for CS# signals that lags ahead SDCLK.
Bit[7:4] Descriptions Bit[7:4] Descriptions
1111 1110 1101 1100 1011 1010 1001 1000
-2.5ns -2.0ns -1.5ns -1.0ns -0.5ns
0111 0110 0101 0100 0011
+1.5ns +2.0ns +2.5ns +3.0ns +3.5ns +4.0ns +4.5ns +5.0ns
0.0ns(default) 0010 +0.5ns +1.0ns 0001 0000
Register 8Dh SDWCLK Control Register Default Value: AAh Access: Read/Write Bit 7:4 Access R/W Description SDWCLK Control for MA / SRAS# / SCAS# / RAMW# This field controls the phase of SDWCLK used for MA / SRAS# / SCAS# / RAMW# signals that lags ahead SDCLK.
Bit[7:4] Descriptions Bit[7:4] Descriptions
1111 1110 1101 1100 1011 1010 1001 1000
-2.5ns -2.0ns -1.5ns -1.0ns -0.5ns
0111 0110 0101 0100 0011
+1.5ns +2.0ns +2.5ns +3.0ns +3.5ns +4.0ns +4.5ns +5.0ns
0.0ns(default) 0010 +0.5ns +1.0ns 0001 0000
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3:0 R/W SDWCLK Control for DQM / MD This field controls the phase of SDWCLK used for DQM / MD signals that lags ahead SDCLK.
Bit[7:4] Descriptions Bit[7:4] Descriptions
1111 1110 1101 1100 1011 1010 1001 1000
-2.5ns -2.0ns -1.5ns -1.0ns -0.5ns
0111 0110 0101 0100 0011
+1.5ns +2.0ns +2.5ns +3.0ns +3.5ns +4.0ns +4.5ns +5.0ns
0.0ns(default) 0010 +0.5ns +1.0ns 0001 0000
Register 8Eh CPU Clock & SDRAM Clock Relationship Default Value: 00h Access: Read/Write Bit 7:2 1 Access R/W R/W Reserved Frequency Relationship of CPU Clock and SDRAM clock. This bit will take effect only if SDRAM Asynchronous Mode, which is controlled by Register 8E bit 0, is enabled. 0: CPU clock frequency is higher than SDRAM clock frequency 1: CPU clock frequency is lower than SDRAM clock frequency 0 R/W SDRAM Synchronous Mode 0: Enable 1: Disable Register 8Fh FBCRCLK/FBCWCLK Control Register Default Value: 2Ah Access: Read/Write Bit Access Description Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:4 R/W FBCRCLK Control This field controls the phase of FBCRCLK that lags behind SDCLK.
Bit[7:4] Descriptions Bit[7:4] Descriptions
1111 1110 1101 1100 1011 1010 1001 1000 3:0 R/W
+6.5ns +6.0ns +5.5ns +5.0ns +4.5ns +4.0ns +3.5ns +3.0ns
0111 0110 0101 0100 0011 0010 0001 0000
+2.5ns +2.0ns +1.5ns +1.0ns +0.5ns +0.0ns (default) -0.5ns -1.0ns
FBCWCLK Control This field controls the phase of FBCWCLK that lags ahead SDCLK.
Bit[7:4] Descriptions Bit[7:4] Descriptions
1111 1110 1101 1100 1011 1010 1001 1000 7.3.8
-2.5ns -2.0ns -1.5ns -1.0ns -0.5ns
0111 0110 0101 0100 0011
+1.5ns +2.0ns +2.5ns +3.0ns +3.5ns +4.0ns +4.5ns +5.0ns
0.0ns(default) 0010 +0.5ns +1.0ns 0001 0000
A.G.P. GART and Page Table Control Registers
Register 90h GART Base Address for Re-mapping Default Value: 00000000h Access: Read/Write Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31:12 R/W A[31:12] for GART Base Address This register provides the start address of the Graphics Address Re-mapping Table Base Locates in main memory. (Please note that the address provides via GART Base is 4KB aligned) 11:0 R/O Reserved
Register 94h Graphic Window Control Default Value: 00h Access: Read/Write This register specifies the size of the graphic window and indicates that whether the Graphic Window Base Address Register and Re-mapping GART Base Address Register contain valid information or not. Bit 7 6:4 Access R/W R/W Reserved Graphic Window Size This field defines the size of the graphic window. The accessibility of GWBA register (Register 10h) is also controlled by this field.
Bits[6:4] Size
Description
000 001 010 011 100 101 110 111 3:2 R/W Reserved
4M 8M 16M 32M 64M 128M 256M Reserved
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1 R/W Graphic Window Base Address (Register 10h) Validation The value of " 1" for this bit indicates that the Graphic Window Base Address specified in GWBA Register(Register 10h) is valid. Otherwise, the address specified in GWBA Register is invalid. 0: Invalid 1: Valid 0 R/W GART Base Address for Re-mapping (Register 90h) Validation The value of " 1" for this bit indicates that the Re-mapping GART Base Address specified in Register 90h is valid. Otherwise, the address specified in Register 90h is invalid. 0: Invalid 1: Valid Register 97h Page Table Cache Control Default Value: 00h Access: Read/Write Page Table Cache is used to speedup the address translation process from graphic address to system memory address. It stores recently used GART entries in the core logic to prevent traffics toward system memory during address translation process. This register controls the characteristic of the page table cache and the address translation mechanism. Bit 7:3 2 Access R/W R/W Reserved GART-Write Invalidate Page Table Cache Control This bit controls SIS630 to avoid using stalled page table cache. When this bit is enabled, SIS630 automatically detects write accesses toward all GART entries and it invalidates the entire page table cache immediately once it observes such an event. If disabled, memory write cycle hits page table entry won' t invalidate the table. 0: Disable 1: Enable 1 R/W Reserved Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 R/W Page Table Cache Enable When this bit is enabled, page table cache will be used for accelerating the address translation process. When this bit is disabled, no GART entries are cached in the page table cache and any address translation is done through memory accesses. 0: Disable 1: Enable Register 98h Page Table Cache Invalidation Control Default Value: 00h Access: Read/Write This register controls the invalidation of page table cache. The invalidation process can apply to the whole page table cache. Bit 7:2 1 Access R/W R/W Reserved Invalidate Page Table Cache Invalidate all page table cache entries when set 1 to this bit. This bit is auto cleared after the invalidation process completed. Reserved Description
0
R/W
Register 9Ch Integrated VGA Control Default Value: 00h Access: Read/Write Bit 7:3 2 Access R/W R/W Reserved VGA Configuration Access Control When this bit set to 0, VGA configuration access can be read and written. When set to 1, VGA configuration can not be accessed. 0: Enable 1: Disable 1 R/W CPU to Integrated VGA Memory Posted Write Control 0: Disable 1: Enable Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 R/W Monochrome Device Adapter(MDA) Existence Control 0: Not exist 1: Exist 7.3.9 DRAM Priority Timer Control Register
Register A0h CPU/PCI-GUI Privilege Timer Default Value: 0000h Access: Read/Write SIS630 maintains the privilege of DRAM usage between CPU/PCI and GUI. When both CPU/PCI and GUI are craving for the resource of system memory, this set of timers provides the adjustment of DRAM bandwidth between these two agents. The operation of the set of timers is explained below. If GUI data transfer has higher privilege over CPU/PCI, GUI high privilege timer decreases every clock when GUI accesses toward system memory is undergoing. If CPU/PCI privilege is higher than GUI, CPU/PCI high privilege timer decreases every clock when CPU/PCI accesses system memory. The privilege relationship between CPU/PCI and GUI is exchanged after the timer expired. CPU/PCI accesses do not affect any one of these two timers if CPU/PCI does not have higher privilege than GUI. In the same way, GUI low priority accesses do not affect timers if GUI device does not have higher privilege than CPU/PCI. Bit 15:8 Access R/W Description Initial Value for GUI High Privilege Timer The timer controls how long GUI data transfer has higher privilege over CPU/PCI for DRAM accesses. Unit: DRAM clock * 4 7:0 R/W Initial Value for CPU/PCI high Privilege Timer The timer controls how long the CPU/PCI has higher privilege over GUI data transfer for DRAM accesses.
Register A2h CPU/PCI-GUI Privilege Timer Control Default Value: 00h Access: Read/Write Bit 7:6 Access R/W Description CPU/PCI-GUI Privilege Timer Control
Bits[7:6] Privilege
00 01 1x Preliminary V.10 Oct.07,1999 114
CPU/PCI High Privilege GUI High Privilege Enable CPU/PCI-GUI Privilege Timer Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5:2 1 R/W R/W Reserved Enhance 3D Performance Control In order to enhance 3D performance, when one of 3D request acquires the DRAM bus, arbiter will mask all other 3D requests until present transaction is finished. 0: Disable 1: Enable 0 R/W Rising AGP Request priority to shorten CPU High Request Waiting time When CPU high priority request is bounded by AGP requests, arbiter will mask the requests that between CPU high priority request and AGP requests until CPU request isn' t bound by AGP requests. 0: Disable 1: Enable Register A3h GUI Grant Timer Default Value: 00h Access: Read/Write Bit 7:4 3:0 Access R/W R/W
Reserved
Description Initial Value of GUI Grant Timer The timer determines the maximum transactions will be done when GUI gets the DRAM and it' s a GUI multi-transaction.
Bit[3:0] Transactions Bit[3:0] Transactions
0000 0001 0010 0011 0100 0101 0110 0111
1 2 3 4 5 6 7 8
1000 1001 1010 1011 1100 1101 1110 1111
9 10 11 12 13 14 15 16
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7.3.10 A.G.P. Control Registers Register C0h A.G.P. Capability Identify Register (ACAPID) Default Value: 00200002h Access: Read Only Bit 31:24 23:20 Access RO RO Reserved A.G.P. revision Major Default value is " 0010b" to indicate that SIS630 conforms to the major revision 2 of A.G.P. interface specification. A.G.P. revision Minor Default value is " 0000b" to indicate that SIS630 conforms to the minor revision 0 of A.G.P. interface specification. Next Capability Default value is " 00h" to indicate the final item. A.G.P. Capability ID Default value is " 02h" to indicate the list item as pertaining to A.G.P. registers. Description
19:16
RO
15:8 7:0
RO RO
Register C4h A.G.P. Status Register Default Value: 1F000203h Access: Read Only Bit 31:24 Access RO Description RQ Field The RQ field contains the maximum number of AGP command requests SIS630 can manage. Default value is " 1Fh" to indicate that the maximum number of A.G.P. command requests SIS630 can manage is 32. 23:10 9 RO RO Reserved SBA Default value is 1 to indicate that SIS630 supports side band addressing. Reserved
8:3
RO
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 2:0 RO Data Rate The RATE field indicates the data transfer rates supported by this device. Default value is " 111b" to indicate SIS630 supports both 1X, 2X and 4X mode. Register C8h A.G.P. Command Register Default Value: 00000000h Access: Read/Write Bit 31:10 9 8 Access R/W R/W R/W Reserved SBA_ENABLE. When set, the side band address mechanism is enabled. AGP_ENABLE. Setting the bit allows the target to accept A.G.P. operations. When cleared, the target ignores incoming A.G.P. operations. Please note that the target must be enabled before the master. Reserved Data Rate One(and only one) bit in the DATA_RATE field must be set to indicate the desired data transfer rate. Bits[1:0] Data Rate
Description
7:3 2:0
R/W R/W
001 010 100 Others
1X Mode 2X Mode 4X Mode Reserved
7.4
Virtual PCI-to-PCI Bridge Registers (Device 2)
Register 00h Vendor ID Default Value: 1039h Access: Read Only The register identifies the manufacturer of the device. SiS is allocated as 1039h by PCI SIG. Bit Access 117 Description Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 15:0 RO Vendor Identification Number
Register 02h Device ID Default Value: 0001h Access: Read Only The device identifier is allocated as 0001h by Silicon Integrated Systems Corp. Bit 15:0 Access RO Description Device Identification Number
Register 04h Command Default Value: 00h Access: Read/Write, Read Only The Command register provides coarse control over a device' s ability to generate and respond to PCI cycles. Bit 15:9 8:6 5 Access RO RO R/W Reserved Reserved Default value is 000b VGA Palette Snoop Enable : Controls the behaviour in the case of CPU access destined to VGA compatible address. The bit affects the destinations of I/O writes issued by the CPU with address 3C6, 3C8, 3C9. 0: Disable 1: Enable 4:3 2 RO R/W Reserved Bus Master Enable Controls the bridge' s ability to operate as a master on the primary interface when forwarding memory or I/O transactions from the secondary interface to the primary interface on behalf of a master on the secondary interface. 0: Disable 1: Enable Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1 R/W Memory Space Enable Controls the forwarding of memory accesses from CPU to A.G.P. When this bit is disabled, the bridge won' t forward any memory accesses to A.G.P. When it is enabled, the bridge forwards CPU memory cycles toward A.G.P. according to standard PCI-to-PCI bridge forwarding rule. 0: Disable 1: Enable 0 R/W I/O Space Enable Controls the forwarding of I/O accesses from CPU to A.G.P. When the bit is disabled, the bridge won' t forward any I/O accesses to A.G.P. When this bit is enabled, the bridge forwards CPU I/O cycles toward A.G.P. according to standard PCI-to-PCI bridge forwarding rule. 0: Disable 1: Enable Register 06h Status Default Value: 00h Access: Read Only This register is reserved since the status information of the primary bus is stored in the status register of Device 0. Bit 15:0 Access RO Reserved Description
Register 08h Revision ID Default Value: 00h Access: Read Only The Revision ID is 00h for our first Revision. Bit 7:0 Access RO Description Revision Identification Number
Register 09h Programming Interface Default Value: 00h Access: Read Only The default value is 00h since no specific register-level programming interface is provided. Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:0 RO Programming Interface
Register 0Ah Sub Class Code Default Value: 04h Access: Read Only The Sub Class Code is 04h for PCI-to-PCI Bridge. Bit 7:0 Access RO Description Sub Class Code
Register 0Bh Base Class Code Default Value: 06h Access: Read Only The value of 06h in this field identifies a bridge device. Bit 7:0 Access RO Base Class Code Description
Register 0Ch Cache Line Size Default Value: 00h Access: Read Only The value of this register is always 00h since the Host Bridge won' t generate the Memory Write and Invalidate command. Bit 7:0 Access RO Cache Line Size Description
Register 0Dh Master Latency Timer (MLT) Default Value: 00h Access: Read Only Bit 7:0 Access RO Description Initial Value for Master Latency Timer Unit: A.G.P. clock
Register 0Eh Header Type Default Value: 01h Access: Read Only The value of 06h identifies PCI-to-PCI Bridge header is being used. Bit 7:0 Access RO Header Type 120 Silicon Integrated Systems Corporation Description
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 0Fh BIST Default Value: 00h Access: Read Only The value is 00h since we don' t support Build-in Self-Test. Bit 7:0 Access RO BIST Description
Register 19h Secondary Bus Number (SBUSN) Default Value: 00h Access: Read/Write This register identifies the bus number assigned to the second bus side of the " virtual" PCIto-PCI Bridge. This field is programmed by the PCI configuration software to allow mapping of configuration cycles to AGP. Bit 7:0 Access R/W Secondary Bus Number Description
Register 1Ah Subordinate Bus Number (SUBUSN) Default Value: 00h Access: Read/Write This register is used to record the number of the highest numbered PCI bus that is behind A.G.P. Bit 7:0 Access R/W Description Subordinate Bus Number Default value is 00h.
Register 1Bh Secondary Master Latency Timer (SMLT) Default Value: 00h Access: Read Only Bit 7:0 Access RO Reserved Description
Register 1Ch I/O Base Default Value: F0h Access: Read/Write, Read Only The I/O Base register defines the bottom address of an address range that is used by SIS630 to determine the timing to forward I/O transactions from CPU to A.G.P. Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:4 R/W I/O Address Base A[15:12] Bits[7:4] controls the CPU to A.G.P. I/O access. SIS630 forwards I/O cycle initiated by CPU to A.G.P. if the address of the cycle meets the following requirement. IO_BASE address IO_LIMIT 3:0 RO Reserved
Register 1Dh I/O Limit Default Value: 00h Access: Read/Write, Read Only The I/O Limit register defines the top address of an address range that is used by SIS630 to determine the timing to forward I/O transactions from CPU to A.G.P. Bit 7:4 Access R/W Description I/O Address Limit A[15:12] Bits[7:4] control the CPU to A.G.P. I/O access. SIS630 forwards I/O cycle initiated by CPU to A.G.P. if the address of the cycle meets the following requirement. IO_BASE address IO_LIMIT 3:0 RO Reserved
Register 1Eh Secondary PCI-PCI Status (SSTS) Default Value: 0000h Access: Read/Write, Read Only The Secondary Status register is similar in function and bit definition to the Status register of device 0 function 0 of SIS630. Bit 15:14 13 Access RO WC Description Reserved Receiver Master Abort When SIS630 terminates a cycle on A.G.P. with master abort, this bit is set to 1. This bit can be cleared by writing a 1 to it. Reserved
12:0
RO
Register 20h Non-prefetchable Memory Base Address (MBASE) Default Value: FFF0h Access: Read/Write, Read Only The register defines the base address of a non-prefetchable memory address range that is used by SIS630 to determine the timing to forward memory transactions from CPU to A.G.P. Preliminary V.10 Oct.07,1999 122 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bit 15:4 Access R/W Description Memory Address Base A[31:20]. Bits[15:4] control the CPU to A.G.P. memory access. SIS630 forwards I/O cycle initiated by CPU to A.G.P. if the address of the cycle meets the following requirement. MBASE address MLIMIT 3:0 RO Reserved
Register 22h Non-prefetchable Memory Limit Address (MLIMIT) Default Value: 0000h Access: Read/Write, Read Only This register defines the top address of a non-prefetchable memory address range that is used by SIS630 to determine the timing to forward memory transactions from CPU to A.G.P. Bit 15:4 Access R/W Description Memory Address Limit A[31:20]. Bits[15:4] control the CPU to A.G.P. memory access. SIS630 forwards I/O cycle initiated by CPU to A.G.P. if the address of the cycle meets the following requirement. MBASE address MLIMIT 3:0 RO Reserved
Register 24h Prefetchable Memory Base Address (PMBASE) Default Value: FFF0h Access: Read/Write, Read Only This register defines the base address of a prefetchable memory address range that is used by SIS630 to determine the timing to forward memory transactions from CPU to A.G.P. Bit 15:4 Access R/W Description Memory Address Base A[31:20]. Bits[15:4] control the CPU to A.G.P. memory access. SIS630 forwards I/O cycle initiated by CPU to A.G.P. if the address of the cycle meets the following requirement. PMBASE address PMLIMIT 3:0 RO Reserved
Register 26h Prefetchable Memory Limit Address (PMLIMIT) Default Value: 0000h Access: Read/Write, Read Only Preliminary V.10 Oct.07,1999 123 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset This register defines the top address of a prefetchable memory address range that is used by SIS630 to determine the timing to forward memory transactions from CPU to A.G.P. Bit 15:4 Access R/W Description Memory Address Limit A[31:20]. Bits[15:4] control the CPU to A.G.P. memory access. SIS630 forwards I/O cycle initiated by CPU to A.G.P. if the address of the cycle meets the following requirement. PMBASE address PMLIMIT 3:0 RO Reserved
Register 3Eh PCI to PCI Bridge Control (BCTRL) Default Value: 0000h Access: Read/Write, Read Only The Bridge Control register provides control extensions to the Command register. Bit 15:4 3 Access RO R/W Reserved. VGA Enable This bit controls the forwarding of transactions initiated by CPU. When this bit is enabled, SIS630 forwards CPU-initiated cycles with the following address to A.G.P. Memory Address: 0A0000h ~ 0BFFFFh I/O Address: 3B0h ~ 3BBh, 3C0 ~ 3DFh 0 : Disable 1 : Enable 2 R/W ISA Enable When Enabled, if I/O addressing the last 768 bytes in each 1KB Block (that is A9 or A8 = 1), this cycle forwards to Primary PCI even if the address is within the range defined by the IOBASE and IOLIMIT. 0 : Disable 1 : Enable 1:0 RO Reserved Description
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8
PCI IDE Configuration Space Register
Device IDE IDSEL AD11 Function Number 0001b
Register 00h Vendor ID Default Value: 1039h Access: Read Only The register identifies the manufacturer of the device. SiS is allocated as 1039h by PCI SIG. Bit 15:0 Access RO Description Vendor Identification Number
Register 02h Device ID Default Value: 5513h Access: Read Only The device identifier is allocated as 5513h by Silicon Integrated Systems Corp. Bit 15:0 Access RO Description Device Identification Number
Register 04h Command Default Value: 0000h Access: Read/Write, Read Only The Command register provides coarse control over a device ability to generate and respond to PCI cycles. Bit 15:3 2 Access RO R/W Description Reserved Bus Master When set, the Bus master function is enabled. It is disabled by default. Memory Space The bit controls the response to memory space accesses. This bit should be programmed as "0". I/O Space When enabled, the built-in IDE will respond to any access of the IDE legacy ports in the compatibility mode, or to any access of the IDE relocated ports in the native mode. Also, any access to the PCI bus master IDE registers are allowed. This bit is zero (disabled) on reset. 125 Silicon Integrated Systems Corporation
1
R/W
0
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 06h Status Default Value: 0000h Access: Read/Write, Read Only, Write Clear The Status register is used to record status information for PCI bus related events. Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set. A bit is reset whenever the register is written, and the data in the corresponding bit location is a 1. For instance, to clear bit 14 and not affect any other bits, write the value 0100_0000_0000_0000b to the register. Bit 15:14 13 Access RO WC Description Reserved These bits are hardware to zero. Master Abort Asserted This bit is set when a PCI bus master IDE transaction is terminated by master abort. While this bit is set, IDE will issue an interrupt request. This bit can be cleared by writing a 1 to it. Received Target Abort The bit is set whenever PCI bus master IDE transaction is terminated with target abort. Signaled Target Abort The bit will be asserted when IDE terminates a transaction with target abort. DEVSEL# Timing DEVT These two bits define the timing of asserting DEVSEL#. The built-in IDE always asserts DEVSEL# in fast timing, and thus the two bits are hardwired to 0 per PCI Spec. Reserved, Read as "0". Reserved Default value is 00h
12
WC
11
RO
10:9
RO
8 7:0
RO RO
Register 08h Revision ID Default Value: D0h Access: Read Only Bit 7:0 Access RO Description Revision Identification Number
Register 09h Programming Interface Default Value: 00h Access: Read Only, Read/Write The default value is 00h since no specific register-level programming interface is provided. Preliminary V.10 Oct.07,1999 126 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bit 7 Access RO Description Master IDE Device This bit is hardwired to one to indicate that the built-in IDE is capable of supporting bus master function. Reserved Secondary IDE Programmable Indicator When the bit is programmed as "1", it means that the primary channel can be programmed to operate in compatible or native mode. When the bit is programmed as "0", the mode is fixed and is determined by the value of bit 2. This bit should be programmed as "1" during the BIOS boot up procedures. Secondary IDE Operating Mode This bit defines the mode that the secondary IDE channel is operating in. Zero corresponds to 'compatibility' while one means native mode. By default, this bit is 0 and is programmable. Primary IDE Programmable Indicator When the bit is programmed as " 1", it means that the primary channel can be programmed to operate in compatible or native mode. When the bit is programmed as " 0", the mode is fixed and is determined by the value of bit 0. This bit should be programmed as "1" during the BIOS boot up procedures. Primary IDE Operating Mode This bit defines the mode that the primary IDE channel is operating in. Zero corresponds to 'compatibility' while one means native mode. By default, this bit is 0 and is programmable.
6:4 3
RO RO
2
R/W
1
RO
0
R/W
Register 0Ah Sub Class Code Default Value: 01h Access: Read Only Bit 7:0 Access RO Description Sub Class Code
Register 0Bh Base Class Code Default Value: 01h Access: Read Only Bit 7:0 Access RO Description Base Class Code
Register 0Ch Cache Line Size Default Value: 00h Preliminary V.10 Oct.07,1999 127 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Access: Bit 7:0 RO Read Only Access Cache Line Size Description
Register 0Dh Latency Timer Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description Initial Value for Latency Timer The default value is 0. Unit: PCI clock
Register 0Eh Header Type Default Value: 80h Access: Read Only Bit 7:0 Access RO Description Header Type
Register 0Fh BIST Default Value: 00h Access: Read Only Bit 7:0 Access RO Description BIST
Register 10h~13h Primary Channel Command Block Base Address Register Register 14h~17h Primary Channel Control Block Base Address Register Register 18h~1Bh Secondary Channel Command Block Base Address Register Register 1Ch~1Fh Secondary Channel Control Block Base Address Register In the native mode, above four registers define the IDE base address for each of the two IDE devices in both the primary and secondary channels respectively. In the compatible mode, the four registers can still be programmed and read out, but it does not affect the IDE address decoding. Register 20h~23h Bus Master IDE Control Register Base Address Offset Register 00h 01h 02h 03h 04-07h Preliminary V.10 Oct.07,1999 Register Access Bus Master IDE Command Register (Primary) Reserved Bus Master IDE Status Register(Primary) Reserved Bus Master IDE PRD (*) Table Pointer (Primary) 128 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 08h 09h 0Ah 0Bh 0C-0Fh *PRD: Physical Region Descriptor Register 24h~2Bh Reserved Register 2C~2Dh Subsystem Vendor ID Default Value: 0000h Access: Read/Write This register can be written once and is used to identify vendor of the subsystem. Register 2Eh~2Fh Subsystem ID Default Value: 0000h Access: Read/Write This register can be written once and is used to identify subsystem ID. Register 30h~3Bh Reserved Register 3Ch Interrupt Line Default value: 00h Access: Read/Write Register 3Dh Interrupt Pin Default value: 00h Access: RO This register is used to tell the drivers or operation systems that which interrupt pin the IDE controller uses. The value of this register is read only and depends on the IDE controller' s operating mode. If either IDE channel operates in Native mode, then this register will be read as " 1", else it will be read as " 0" to indicate no interrupt pin is used. Register 3Eh~3Fh Reserved Register 40h IDE Primary Channel/Master Drive Data Recovery Time Control Default Value: 00h Access: Read/Write Bit Access Description Bus Master IDE Command Register (Secondary) Reserved Bus Master IDE Status Register (Secondary) Reserved Bus Master IDE PRD (*) Table Pointer (Secondary)
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7 R/W Test mode for internal use only 0: Normal mode 1: Test mode This test mode for recovery and active timer counter. Test mode for internal use only 0: Normal mode 1: Test mode This test mode for prefetch byte counter. Reserved Recovery Time 0000: 12 PCICLK 0001: 1 PCICLK 0010: 2 PCICLK 0011: 3 PCICLK 0100: 4 PCICLK 0101: 5 PCICLK 0110: 6 PCICLK 0111: 7 PCICLK 1000: 8 PCICLK 1001: 9 PCICLK 1010: 10 PCICLK 1011: 11 PCICLK 1100: 13 PCICLK 1101: 14 PCICLK 1110: 15 PCICLK 1111: 15 PCICLK
6
R/W
5:4 3:0
RO R/W
Register 41h IDE Primary Channel/Master Drive Data Active Time Control Default Value: 00h Access: Read/Write Bit 7 Access R/W Description Ultra DMA Mode Control 0: Disable 1: Enable Ultra DMA 33/66 cycle time Select 000: Reserved 001: Cycle time of 2 CLK clocks for data out 010: Cycle time of 3 CLK clocks for data out 011: Cycle time of 4 CLK clocks for data out 100: Cycle time of 5 CLK clocks for data out 101: Cycle time of 6 CLK clocks for data out 110: Cycle time of 7 CLK clocks for data out 111: Cycle time of 8 CLK clocks for data out Note : 2 CLK = 1 PCICLK 3 RO Reserved 130 Silicon Integrated Systems Corporation
6:4
R/W
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 2:0 R/W Data Active Time Control 000: 8 PCICLK 010: 2 PCICLK 100: 4 PCICLK 110: 6 PCICLK
001: 1 PCICLK 011: 3 PCICLK 101: 5 PCICLK 111: 12 PCICLK
Register 42h IDE Primary Channel/Slave Drive Data Recovery Time Control Default Value: 00h Access: Read/Write Bit 7:4 3:0 Access RO R/W Description Reserved Recovery Time 0000: 12 PCICLK 0010: 2 PCICLK 0100: 4 PCICLK 0110: 6 PCICLK 1000: 8 PCICLK 1010: 10 PCICLK 1100: 13 PCICLK 1110: 15 PCICLK
0001: 1 PCICLK 0011: 3 PCICLK 0101: 5 PCICLK 0111: 7 PCICLK 1001: 9 PCICLK 1011: 11 PCICLK 1101: 14 PCICLK 1111: 15 PCICLK
Register 43h IDE Primary Channel/Slave Drive Data Active Time Control Default Value: 00h Access: Read/Write Bit 7 Access R/W Description Ultra DMA Mode Control 0: Disable 1: Enable
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 6:4 R/W Ultra DMA 33/66 cycle time Select 000: Reserved 001: Cycle time of 2 CLK clocks for data out 010: Cycle time of 3 CLK clocks for data out 011: Cycle time of 4 CLK clocks for data out 100: Cycle time of 5 CLK clocks for data out 101: Cycle time of 6 CLK clocks for data out 110: Cycle time of 7 CLK clocks for data out 111: Cycle time of 8 CLK clocks for data out Note : 2 CLK = 1 PCICLK Reserved Data Active Time Control 000: 8 PCICLK 001: 1 PCICLK 010: 2 PCICLK 011: 3 PCICLK 100: 4 PCICLK 101: 5 PCICLK 110: 6 PCICLK 111: 12 PCICLK
3 2:0
RO R/W
Register 44h IDE Secondary Channel/Master Drive Data Recovery Time Control Default Value: 00h Access: Read/Write Bit 7:4 3:0 Access RO R/W Description Reserved Recovery Time 0000: 12 PCICLK 0010: 2 PCICLK 0100: 4 PCICLK 0110: 6 PCICLK 1000: 8 PCICLK 1010: 10 PCICLK 1100: 13 PCICLK 1110: 15 PCICLK
0001: 1 PCICLK 0011: 3 PCICLK 0101: 5 PCICLK 0111: 7 PCICLK 1001: 9 PCICLK 1011: 11 PCICLK 1101: 14 PCICLK 1111: 15 PCICLK
Register 45h IDE Secondary Channel/Master Drive Data Active Time Control Default Value: 00h Access: Read/Write Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7 R/W Ultra DMA Mode Control 0: Disable 1: Enable Ultra DMA 33/66 cycle time Select 000: Reserved 001: Cycle time of 2 CLK clocks for data out 010: Cycle time of 3 CLK clocks for data out 011: Cycle time of 4 CLK clocks for data out 100: Cycle time of 5 CLK clocks for data out 101: Cycle time of 6 CLK clocks for data out 110: Cycle time of 7 CLK clocks for data out 111: Cycle time of 8 CLK clocks for data out Note : 2 CLK = 1 PCICLK 3 2:0 RO R/W Reserved Data Active Time Control 000: 8 PCICLK 001: 1 PCICLK 010: 2 PCICLK 011: 3 PCICLK 100: 4 PCICLK 101: 5 PCICLK 110: 6 PCICLK 111: 12 PCICLK
6:4
R/W
Register 46h IDE Secondary Channel/Slave Drive Data Recovery Time Control Default Value: 00h Access: Read/Write Bit 7:4 3:0 Access RO R/W Description Reserved Recovery Time 0000: 12 PCICLK 0010: 2 PCICLK 0100: 4 PCICLK 0110: 6 PCICLK 1000: 8 PCICLK 1010: 10 PCICLK 1100: 13 PCICLK 1110: 15 PCICLK
0001: 1 PCICLK 0011: 3 PCICLK 0101: 5 PCICLK 0111: 7 PCICLK 1001: 9 PCICLK 1011: 11 PCICLK 1101: 14 PCICLK 1111: 15 PCICLK
Register 47h Default Value:
IDE Secondary Channel/Slave Drive Data Active Time Control 00h 133 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Access: Bit 7 Read/Write Access R/W Description Ultra DMA Mode Control 0: Disable 1: Enable Ultra DMA 33/66 cycle time Select 000: Reserved 001: Cycle time of 2 CLK clocks for data out 010: Cycle time of 3 CLK clocks for data out 011: Cycle time of 4 CLK clocks for data out 100: Cycle time of 5 CLK clocks for data out 101: Cycle time of 6 CLK clocks for data out 110: Cycle time of 7 CLK clocks for data out 111: Cycle time of 8 CLK clocks for data out Note : 2 CLK = 1 PCICLK 3 2:0 RO R/W Reserved Data Active Time Control 000: 8 PCICLK 010: 2 PCICLK 100: 4 PCICLK 110: 6 PCICLK
6:4
R/W
001: 1 PCICLK 011: 3 PCICLK 101: 5 PCICLK 111: 12 PCICLK
Register 48h IDE Status Register Default Value: 00h Access: Read/Write Bit 7:6 5 Access RO RO Reserved Channel 1 Cable Type Status (via CBLIDB signal) 0: 80 pins cable type 1: 40 pins cable type Channel 0 Cable Type Status (via CBLIDA signal) 0: 80 pins cable type 1: 40 pins cable type Description
4
RO
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3:2 R/W PCI Read Request Threshold Setting 00: PCI Request asserted when FIFO is 62.5% full during prefetch cycles. 01: PCI Request asserted when FIFO is 50.0% full during prefetch cycles. 10: PCI Request asserted when FIFO is 25.0% full during prefetch cycles. 11: PCI Request asserted when FIFO is 12.5% full during prefetch cycles. PCI Write Request Threshold Setting 00: PCI Request asserted when FIFO is 12.5% full during prefetch cycles. 01: PCI Request asserted when FIFO is 25.0% full during prefetch cycles. 10: PCI Request asserted when FIFO is 50.0% full during prefetch cycles. 11: PCI Request asserted when FIFO is 62.5% full during prefetch cycles.
1:0
R/W
Register 49h
Reserved
Register 4Ah IDE General Control Register 0 Default Value: 00h Access: Read/Write Bit 7 Access R/W Description Bus Master generates PCI burst cycles Control 0: Disable 1: Enable Reserved Fast post-write control 0: Disabled 1: Enabled (Recommended) Test Mode for internal use only 0: Normal Mode 1: Test Mode When this bit is set 1, the IRQ of HD drive would pass direct to 8259. On the others hand, IDE would gate IRQ until IDE FIFO is empty under abnormal operation. Reserved 135 Silicon Integrated Systems Corporation
6 5
R/W R/W
4
R/W
3
R/W
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 2 R/W IDE Channel 1 Enable Bit 0: Disabled 1: Enabled 1 R/W IDE Channel 0 Enable Bit 0: Disabled 1: Enabled Reserved
0
R/W
Register 4Bh IDE General Control register 1 Default Value: 00h Access: Read/Write Bit 7 Access R/W Description Enable Postwrite of the Slave Drive in Channel 1 0: Disabled 1: Enabled Enable Postwrite of the Master Drive in Channel 1 0: Disabled 1: Enabled Enable Postwrite of the Slave Drive in Channel 0 0: Disabled 1: Enabled Enable Postwrite of the Master Drive in Channel 0 0: Disabled 1: Enabled Enable Prefetch of the Slave Drive in Channel 1 0: Disabled 1: Enabled Enable Prefetch of the Master Drive in Channel 1 0: Disabled 1: Enabled Enable Prefetch of the Slave Drive in Channel 0 0: Disabled 1: Enabled Enable Prefetch of the Master Drive in Channel 0 0: Disabled 1: Enabled 136 Silicon Integrated Systems Corporation
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
(Following two 16-bit wide registers define the prefetching length of each IDE channel Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset respectively.) Register 4Ch~4Dh Prefetch Count of Primary Channel Default Value: 0000h Access: Read/Write Bit 15:0 Access R/W Description Prefetch Count of Primary Channel The Count (in bytes) of IDE prefetch. The maximum value can be programmed is 512. (Default value is 512)
Register 4Eh~4Fh Prefetch Count of Secondary Channel Default Value: 0000h Access: Read/Write Bit 15:0 Access R/W Description Prefetch Count of Secondary Channel The Count (in bytes) of IDE prefetch. The maximum value can be programmed is 512. (Default value is 512)
Register 50h~51h Reserved Default Value: 0000h Access: Read/Write Bit 15:0 Access R/W Description Reserved
Register 52h IDE Miscellaneous Control Register Default Value: 00h Access: Read/Write Bit 7:5 4 Access RO R/W Description Reserved IDE I/O Buffer Driving Strength Control 0: strong 1: weak Reserved Control of IDE Programmable Indicator (Reg. 09 bit 1 and 3) 0: IDE register 09 bit 1 and 3 would be read as " 1 1: IDE register 09 bit 1 and 3 would be read as " 0", and register 09 bit 0 and 2 would be read as " 0". It means IDE controller can only operate in Compatibility mode.
3 2
R/W R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1 R/W Test Mode for internal use only 0 : Normal Mode 1 : Test Mode If this bit is set as 1, IDE controller would reset IDE FIFO pointer when 8 bit command is forward to HDs driver. This bit would work on the condition that the transferring byte count of OS is not equal to the byte count received by HDs driver. Test mode for Internal use only 0: The value of register 3D bit 0 would depend on both channels' operating mode. 1: The value of register 3D bit 0 would be read as " 0".
0
R/W
8.1
Offset Registers for PCI Bus Master IDE Control Registers
The PCI Bus master IDE Registers use 16 bytes of I/O Space. These registers can be accessed through I/O R/W to the address defined in the Bus Master IDE control register Base Address in the PCI IDE Configuration space. The base address is also defined in Register 20h~23h of PCI IDE configuration space. Register 00h Bus Master Primary IDE Command Register Default Value: 00h Access: Read/Write Bit 7:4 6:5 Access RO R/W Description Reserved. Return 0 on reads. Read or Write Control This bit defines the R/W control of the bus master transfer. When set to zero, PCI bus master reads are conducted. When set to one, PCI bus master writes are conducted. Reserved Start/Stop Bus Master The SiS Chip built-in IDE Controller enables its bus master operation whenever it detects this bit changing from a zero to a one. The operation can be halted by writing zero to this bit.
2:1 0
RO R/W
Register 01h
Reserved
Register 02h Bus Master Primary IDE Status Register Default Value: 00h Access: Read/Write Bit Access 138 Description Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7 RO Simplex Only This bit is hardwired to zero to indicate that both bus master channels can be operated at a time. Drive 1 DMA Capable This R/W bit can be set by BIOS or driver to indicate that drive 1 for this channel is capable of DMA transfers. Drive 0 DMA Capable This R/W bit can be set by BIOS or driver to indicate that drive 0 for this channel is capable of DMA transfers. Reserved. Return 0 on reads Interrupt The bit is set by the rising edge of the IDE interrupt line to indicate that all data transferred from the drive is visible in the system memory. Writing a '1' to this bit can reset it. Error This bit is set when the IDE controller encounters an error during data transferring to/from memory. Bus Master IDE Device Active This bit is set when the start bit in the command register is set. It can be cleared when the last transfer of a region is performed, or the start bit is reset.
6
R/W
5
R/W
4:3 2
RO R/W
1
RO
0
R/W
Register 03h
Reserved
Register 04h~07h Bus Master Primary IDE PRD Table Pointer Register This 32-bit register contains address pointing to the starting address of the PRD table. Default Value: 00000000h Access: Read/Write Bit 31:2 1:0 Access R/W R/W Description Base Address of the PRD Table Reserved
*PRD: Physical Region Descriptor Register 08h Bus Master Secondary IDE Command Register Default Value: 00h Access: Read/Write Bit 7:4 Access RO Description Reserved. Return 0 on reads. 139 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3 R/W Read or Write Control. This bit defines the R/W control of the bus master transfer. When set to " 0", PCI bus master reads are conducted. When set to " 1", PCI bus master writes are conducted. Reserved Start/Stop Bus Master The SiS chip built-in IDE Controller enables its bus master operation whenever it detects this bit changing from a zero to a one. The operation can be halted by writing a zero to this bit.
2:1 0
RO R/W
Register 09h
Reserved
Register 0Ah Bus Master Secondary IDE Status Register Default Value: 00h Access: Read/Write Bit 7 Access RO Description Simplex Only This bit is hardwired to zero to indicate that both bus master channels can be operated at a time. Drive 1 DMA Capable This R/W bit can be set by BIOS or driver to indicate that drive 1 for this channel is capable of DMA transfers. Drive 0 DMA Capable This R/W bit can be set by BIOS or driver to indicate that drive 0 for this channel is capable of DMA transfers. Reserved. Return 0 on reads Interrupt The bit is set by the rising edge of the IDE interrupt line to indicate that all data transferred from the drive is visible in the system memory. Writing a '1' to this bit can reset it. Error This bit is set when the IDE controller encounters an error during data transferring to/from memory. Bus Master IDE Device Active This bit is set when the start bit in the command register is set. It can be cleared when the last transfer of a region is performed, or the start bit is reset.
6
R/W
5
R/W
4:3 2
RO R/W
1
RO
0
R/W
Register 0Bh
Reserved
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 0Ch~0Fh Bus Master Secondary IDE PRD Table Pointer Register This 32-bit register contains address pointing to the starting address of the PRD table. Default Value: 00000000h Access: Read/Write Bit 31:2 1:0 Access R/W R/W Description Base Address of the PRD Table Reserved
*PRD: Physical Region Descriptor
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
9
9.1
Register Summary / Description - Graphics
General Registers
9.1.1 Miscellaneous Output Registers Register Type: Read/Write Read Port: 3CC Write Port: 3C2 Default: 00h D7 Vertical Sync Polarity 0: Select 'positive vertical sync' 1: Select 'negative vertical sync' D6 Horizontal Sync Polarity 0: Select 'positive horizontal sync' 1: Select 'negative horizontal sync' Table 9.1-1 Sync Polarity vs. Vertical Screen Resolution D7 0 0 1 1 D5 D6 0 1 0 1 Odd/Even Page 0: Select low page of memory 1: Select high page of memory Reserved Clock Select Table 9.1-2 Table for Video Clock Selection D3 0 0 1 1 D1 D2 0 1 0 1 DCLK 25.175 MHz 28.322 MHz Don't Care For internal clock generator. EGA 200 Lines 350 Lines Invalid Invalid VGA Invalid 400 Lines 350 Lines 480 Lines
D4 D[3:2]
D0
Display RAM Enable 0: Disable processor access to video RAM 1: Enable processor access to video RAM I/O Address Select 0: Sets addresses for monochrome emulation 142 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1: Sets addresses for color graphics emulation Feature Control Register Register Type: Read/Write Read Port: 3CA Write Port: 3BA/3DA Default: 00h D[7:4] Reserved (0) D3 Vertical Sync Select 0: Normal Vertical Sync output to monitor 1: [Vertical Sync OR Vertical Display Enable] output to monitor D[2:0] Reserved (0) Input Status Register 0 Register Type: Read only Read Port: 3C2 Default: 00h D7 Vertical Retrace Interrupt Pending 0: Cleared 1: Pending D[6:5] Reserved D4 Switch Sense D[3:0] Reserved Input Status Register 1 Register Type: Read only Read Port: 3BA/3DA Default: 00h D[7:6] Reserved D[5:4] Diagnostic Table 9.1-3 Table for Video Read-back Through Diagnostic Bit (I) Color Plane Enable Register D5 D4 0 0 1 1 0 1 0 1 Input Status Register 1 D5 D4 Red Secondary Red Secondary Blue Unused Blue Secondary Green Green Unused
Table 9.1-4 Table for Video Read-back Through Diagnostic Bit (II) Preliminary V.10 Oct.07,1999 143 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Color Plane Enable Register D4 0 0 1 1 D3 0 1 0 1 Vertical Trace 0: Inactive 1: Active Reserved Display Enable Not 0: Display period 1: Retrace period Input Status Register 1 D4 P2 P5 P3 P7 P0 P4 P1 P6
D5
D5
D[2:1] D0
VGA Enable Register Register Type: Read/Write Read/Write Port: 3C3 Default: 00h D0 VGA Enable 0: Disable 1: Enable Segment Selection Register 0 Register Type: Read/Write Read/Write Port: 3CD Default: 00h D[7:0] Segment Selection Write Bit[7:0] Segment Selection Register 1 Register Type: Read/Write Read/Write Port: 3CB Default: 00h D[7:0] Segment Selection Read Bit[7:0]
9.2
CRT Controller Registers
CRT Controller Index Register Register Type: Read/Write Read/Write Port: 3B4/3D4 Preliminary V.10 Oct.07,1999 144 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Default: D[7:0] 00h CRT Controller Index - 00h ~ 18h for standard VGA - 19h ~ 26h for SiS extended CRT registers Table 9.2-1 Table of CRT Controller Registers Index (3B4/3D4) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 1Bh 1Ch 1Dh 22h Preliminary V.10 Oct.07,1999 CRT Controller Registers (3B5/3D5) Horizontal Total Horizontal Display Enable End Horizontal Blank Start Horizontal Blank End Horizontal Retrace Start Horizontal Retrace End Vertical Total Overflow Register Preset Row Scan Max Scan Line/Text Character Height Text Cursor Start Text Cursor End Screen Start Address High Screen Start Address Low Text Cursor Location High Text Cursor Location Low Vertical Retrace Start Vertical Retrace End Vertical Display Enable End Screen Offset Underline Location Vertical Blank Start Vertical Blank End Mode Control Line Compare CRT horizontal counter read-back CRT vertical counter read back CRT overflow counter read back Graphics Data Latch Read-back Register 145 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 24h 26h Attribute Controller Toggle Read-back Register Attribute Controller Index Read-back Register
CR0: Horizontal Total Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 00h Default: 00h D[7:0] Horizontal Total Bit[7:0] CR1: Horizontal Display Enable End Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 01h Default: 00h D[7:0] Horizontal Display Enable End Bit[7:0] CR2: Horizontal Blank Start Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 02h Default: 00h D[7:0] Horizontal Blank Start Bit[7:0] CR3: Horizontal Blank End Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 03h Default: 00h D7 Reserved D[6:5] Display Skew Control Bit[1:0] 00: No skew 01: Skew 1 character 10: Skew 2 characters 11: Skew 3 characters D[4:0] Horizontal Blank End Bit[4:0] CR4: Horizontal Retrace Start Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 04h Default: 00h D[7:0] Horizontal Retrace Start Bit[7:0] CR5: Horizontal Retrace End Register Type: Read/Write Preliminary V.10 Oct.07,1999 146 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Read/Write Port: 3B5/3D5, Index 05h Default: 00h D7 Horizontal Blank End Bit[5] D[6:5] Horizontal Retrace Delay Bit[1:0] 00: Skew 0 character clock 01: Skew 1 character clock 10: Skew 2 character clocks 11: Skew 3 character clocks D[4:0] Horizontal Retrace End Bit[4:0] CR6: Vertical Total Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 06h Default: 00h D[7:0] Vertical Total Bit[7:0] CR7: Overflow Register Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 07h Default: 00h D7 Vertical Retrace Start Bit[9] D6 Vertical Display Enable End Bit[9] D5 Vertical Total Bit[9] D4 Line Compare Bit[8] D3 Vertical Blank Start Bit[8] D2 Vertical Retrace Start Bit[8] D1 Vertical Display Enable End Bit[8] D0 Vertical Total Bit[8] CR8: Preset Row Scan Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 08h Default: 00h D7 Reserved D[6:5] Byte Panning Control Bit[1:0] D[4:0] Preset Row Scan Bit[4:0] CR9: Maximum Scan Line/Text Character Height Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 09h Default: 00h Preliminary V.10 Oct.07,1999 147 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset D7 Double Scan 0: Disable 1: Enable 400 lines display Line Compare Bit[9] Vertical Blank Start Bit[9] Character Cell Height Bit[4:0]
D6 D5 D[4:0]
CRA: Text Cursor Start Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 0Ah Default: 00h D[7:6] Reserved D5 Text Cursor Off 0: Text Cursor On 1: Text Cursor Off D[4:0] Text Cursor Start Bit[4:0] CRB: Text Cursor End Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 0Bh Default: 00h D7 Reserved D[6:5] Text Cursor Skew 00: No skew 01: Skew one character clock 10: Skew two character clocks 11: Skew three character clocks D[4:0] Text Cursor End Bit[4:0] CRC: Screen Start Address High Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 0Ch Default: 00h D[7:0] Screen Start Address Bit[15:8] CRD: Screen Start Address Low Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 0Dh Default: 00h D[7:0] Screen Start Address Bit[7:0] Preliminary V.10 Oct.07,1999 148 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset CRE: Text Cursor Location High Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 0Eh Default: 00h D[7:0] Text Cursor Location Bit[15:8] CRF: Text Cursor Location Low Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 0Fh Default: 00h D[7:0] Text Cursor Location Bit[7:0] CR10: Vertical Retrace Start Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 10h Default: 00h D[7:0] Vertical Retrace Start Bit[7:0] CR11: Vertical Retrace End Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 11h Default: 00h D7 Write Protect for CR0 to CR7 0: Disable Write Protect 1: Enable Write Protect D6 Alternate Refresh Rate 0: Selects three refresh cycles per scanline 1: Selects five refresh cycles per scanline D5 Vertical Interrupt Enable 0: Enable 1: Disable D4 Vertical Interrupt Clear 0: Clear 1: Not Clear D[3:0] Vertical Retrace End Bit[3:0] CR12: Vertical Display Enable End Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 12h Default: 00h D[7:0] Vertical Display Enable End Bit[7:0] Preliminary V.10 Oct.07,1999 149 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset CR13: Screen Offset Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 13h Default: 00h D[7:0] Screen Offset Bit[7:0] CR14: Underline Location Register Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 14h Default: 00h D7 Reserved D6 Double-word Mode Enable 0: Disable 1: Enable D5 Count by 4 0: Disable 1: Enable D[4:0] Underline Location Bit[4:0] CR15: Vertical Blank Start Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 15h Default: 00h D[7:0] Vertical Blank Start Bit[7:0] CR16: Vertical Blank End Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 16h Default: 00h D[7:0] Vertical Blank End Bit[7:0] CR17: Mode Control Register Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 17h Default: 00h D7 Hardware Reset 0: Disable horizontal and vertical retrace outputs 1: Enable horizontal and vertical retrace outputs D6 Word/Byte Address Mode 0: Set the memory address mode to word 1: Set the memory address mode to byte Preliminary V.10 Oct.07,1999 150 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset D5 Address Wrap 0: Disable the full 256K of memory 1: Enable the full 256K of memory Reserved Count by Two 0: Byte refresh 1: Word refresh Horizontal Retrace Select 0: Normal 1: Double Scan RA1 replace MA14 0: Enable 1: Disable RA0 replace MA13 0: Enable 1: Disable
D4 D3
D2
D1
D0
CR18: Line Compare Register Register Type: Read/Write Read/Write Port: 3B5/3D5, Index 18h Default: 00h D[7:0] Line Compare Bit[7:0] CR1B: CRT Horizontal Counter Read Back Register Type: Read Only Read/Write Port: 3B5/3D5, Index 1Bh Default: xxh D[7:0] CRT horizontal counter bit[7:0] CR1C: CRT Vertical Counter Read Back Register Type: Read Only Read/Write Port: 3B5/3D5, Index 1Ch Default: xxh D[7:0] CRT vertical counter bit[7:0] CR1D: CRT Overflow Counter Read Back Register Type: Read Only Read/Write Port: 3B5/3D5, Index 1Dh Default: xxh D[7:5] Reserved D4 CRT horizontal counter bit 8 Preliminary V.10 Oct.07,1999 151 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset D3 Reserved D[2:0] CRT vertical counter bit[10:8] Note: The horizontal and vertical counter value will be latched when read register CR20. So the three registers value should be read after read CR20. CR1E: Extended Signature Read-Back Register 2 Register Type: Read Only Read/Write Port: 3B5/3D5, Index 1Eh Default: xxh D[7:0] Signature read-back bit[23:16] CR20: CRT Counter Trigger Port Register Type: Read Only Read/Write Port: 3B5/3D5, Index 20h Default: xxh D[7:0] Reserved CR24: Attribute Controller Toggle Read-back Register Register Type: Read Only Read/Write Port: 3B5/3D5, Index 24h Default: xxh D7 Attribute Controller Toggle D[6:0] Reserved CR26: Attribute Controller Index Read-back Register Register Type: Read Only Read/Write Port: 3B5/3D5, Index 26h Default: xxh D[7:6] Reserved D5 Video Enable D[4:0] Attribute Controller Index bit[8:4]
9.3
Sequencer Registers
Sequencer Index Register Register Type: Read/Write Read/Write Port: 3C4 Default: 00h D[7:6] Reserved D[5:0] Sequencer Index Bit[5:0] Preliminary V.10 Oct.07,1999 152 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
Table 9.3-1 Table of Sequencer Registers Index (3C4) 00 01 02 03 04 SR0: Reset Register Register Type: Read/Write Read/Write Port: 3C5, Index 00h Default: 00h D[7:2] Reserved D1 Synchronous reset 0: Reset 1: Normal D0 Asynchronous reset 0: Reset 1: Normal SR1: Clock Mode Register Register Type: Read/Write Read/Write Port: 3C5, Index 01h Default: 00h D[7:6] Reserved D5 Screen Off 0: Display On 1: Display Off D4 Shifter Load 32 enable 0: Disable 1: Data shifter loaded every 4th Character Clock D3 Dot Clock Divide by 2 enable 0: Disable 1: Video Clock is divided by 2 to generate Dot Clock D2 Shifter Load 16 (while D4=0) 0: Disable 1: Data shifter loaded every 2nd Character Clock D1 Reserved D0 8/9 Dot Clock Preliminary V.10 Oct.07,1999 153 Silicon Integrated Systems Corporation Sequencer Register (3C5) Reset Register Clock Mode Color Plane Write Enable Character Generator Select Memory Mode
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0: Dot Clock is divided by 9 to generate Character Clock 1: Dot Clock is divided by 8 to generate Character Clock SR2: Color Plane Write Enable Register Register Type: Read/Write Read/Write Port: 3C5, Index 02h Default: 00h D[7:4] Reserved D3 Plane 3 write enable 0: Disable 1: Enable D2 Plane 2 write enable 0: Disable 1: Enable D1 Plane 1 write enable 0: Disable 1: Enable D0 Plane 0 write enable 0: Disable 1: Enable SR3: Character Generator Select Register Register Type: Read/Write Read/Write Port: 3C5, Index 03h Default: 00h D[7:6] Reserved D5 Character generator table B select Bit[2] D4 Character generator table A select Bit[2] D[3:2] Character generator table B select Bit[1:0] D[1:0] Character generator table A select Bit[1:0] Table 9.3-2 Table of Selecting Active Character Generator D5 D4 0 0 0 0 1 1 D3 D1 0 0 1 1 0 0 D2 D0 0 1 0 1 0 1 154 Used when text attribute bit 3 is 1 Used when text attribute bit 3 is 0 Character Table 1 Character Table 2 Character Table 3 Character Table 4 Character Table 5 (VGA only) Character Table 6 (VGA only) Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1 1 1 1 0 1 Character Table 7 (VGA only) Character Table 8 (VGA only)
SR4: Memory Mode Register Register Type: Read/Write Read/Write Port: 3C5, Index 04h Default: 00h D[7:4] Reserved D3 Chain-4 Mode enable 0: Disable 1: Enable D2 Odd/Even Mode enable 0: Enable 1: Disable D1 Extended Memory 0: Select 64K 1: Select 256K D0 Reserved
9.4
Graphics Controller Registers
Graphics Controller Index Register Register Type: Read/Write Read/Write Port: 3CE Default: 00h D[7:4] Reserved D[3:0] Graphics Controller Index Bit[3:0] Table 9.4-1 Table of Graphics Controller Registers Index (3CE) 00 01 02 03 04 05 06 07 08 Preliminary V.10 Oct.07,1999 Graphics Controller Register (3CF) Set/Reset Register Set/Reset Enable Register Color Compare Register Data Rotate & Function Select Read Plane Select Register Mode Register Miscellaneous Register Color Don't Care Register Bit Mask Register 155 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset GR0: Set/Reset Register Register Type: Read/Write Read/Write Port: 3CF, Index 00h Default: 00h D[7:4] Reserved D3 Set/Reset Map for plane 3 D2 Set/Reset Map for plane 2 D1 Set/Reset Map for plane 1 D0 Set/Reset Map for plane 0 GR1: Set/Reset Enable Register Register Type: Read/Write Read/Write Port: 3CF, Index 01h Default: 00h D[7:4] Reserved D3 Enable Set/Reset for plane 3 0: Disable 1: Enable D2 Enable Set/Reset for plane 2 0: Disable 1: Enable D1 Enable Set/Reset for plane 1 0: Disable 1: Enable D0 Enable Set/Reset for plane 0 0: Disable 1: Enable GR2: Color Compare Register Register Type: Read/Write Read/Write Port: 3CF, Index 02h Default: 00h D[7:4] Reserved D3 Color Compare Map for plane 3 D2 Color Compare Map for plane 2 D1 Color Compare Map for plane 1 D0 Color Compare Map for plane 0 GR3: Data Rotate/Function Select Register Register Type: Read/Write Preliminary V.10 Oct.07,1999 156 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Read/Write Port: 3CF, Index 03h Default: 00h D[7:5] Reserved D[4:3] Function Select Table 9.4-2 Table of Function Select D4 0 0 1 1 D[2:0] D2 0 0 0 0 1 1 1 1 D3 0 1 0 1 Function write data unmodified write data AND processor latches write data OR processor latches write data XOR processor latches
Rotate Count Table 9.4-3 Table of Rotate Count D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Right Rotation none 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits
GR4: Read Plane Select Register Register Type: Read/Write Read/Write Port: 3CF, Index 04h Default: 00h D[7:2] Reserved D[1:0] Read Plane Select bit 1, 0 00: Plane 0 01: Plane 1 10: Plane 2 11: Plane 3 GR5: Mode Register Register Type: Read/Write Read/Write Port: 3CF, Index 05h Default: 00h D7 Reserved Preliminary V.10 Oct.07,1999 157 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset D6 256-color Mode 0: Disable 1: Enable Shift Register Mode 0: Configure shift register to be EGA compatible 1: Configure shift register to be CGA compatible Odd/Even Addressing Mode enable 0: Disable 1: Enable Read Mode 0: Map Select Read 1: Color Compare Read Reserved Write mode
D5
D4
D3
D2 D[1:0]
Table 9.4-4 Table for Write Mode D1 0 0 1 1 D0 0 1 0 1 Mode Selected Write Mode 0: Direct processor write (Data Rotate, Set/Reset may apply). Write Mode 1: Use content of latches as write data. Write Mode 2: Color Plane n(0-3) is filled with the value of bit m in the processor write data. Write Mode 3: Color Plane n(0-3) is filled with 8 bits of the color value contained in the Set/Reset Register for that plane. The Enable Set/Reset Register is not effective. Processor data will be AND with Bit Mask Register content to form new bit mask pattern. (data rotate may apply).
GR6: Miscellaneous Register Register Type: Read/Write Read/Write Port: 3CF, Index 06h Default: 00h D[7:4] Reserved D[3:2] Memory Address Select Table 9.4-5 Table of Memory Address Select D3 0 0 D2 0 1 158 Address Range A0000 to BFFFF A0000 to AFFFF Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1 1 D1 0 1 Chain Odd And Even Maps 0: Disable 1: Enable Graphics Mode Enable 0: Select alphanumeric mode 1: Select graphics mode B0000 to B7FFF B8000 to BFFFF
D0
GR7: Color Don't Care Register Register Type: Read/Write Read/Write Port: 3CF, Index 07h Default: 00h D[7:4] Reserved D3 Plane 3 Don't Care 0: Disable color comparison 1: Enable color comparison D2 Plane 2 Don't Care 0: Disable color comparison 1: Enable color comparison D1 Plane 1 Don't Care 0: Disable color comparison 1: Enable color comparison D0 Plane 0 Don't Care 0: Disable color comparison 1: Enable color comparison GR8: Bit Mask Register Register Type: Read/Write Read/Write Port: 3CF, Index 08h Default: 00h D[7:0] Bit Mask Enable Bit[7:0]
9.5
Attribute Controller and Video DAC Registers
Attribute Controller Index Register Register Type: Read/Write Read Port: 3C0 Write Port: 3C0 Default: 00h Preliminary V.10 Oct.07,1999 159 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset D[7:6] D5 Reserved Palette Address Source 0: From CPU 1: From CRT Attribute Controller Index Bit[4:0] (00h-14h) Table 9.5-1 Table of Attribute Controller Registers Index (3C0) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h AR0~ARF: Palette Registers Register Type: Read/Write Read Port: 3C1, Index 00h ~ 0Fh Write Port: 3C0, Index 00h ~ 0Fh Default: 00h D[7:6] Reserved D[5:0] Palette Entries Attribute Controller Register (3C0) Color Palette Register 0 Color Palette Register 1 Color Palette Register 2 Color Palette Register 3 Color Palette Register 4 Color Palette Register 5 Color Palette Register 6 Color Palette Register 7 Color Palette Register 8 Color Palette Register 9 Color Palette Register 10 Color Palette Register 11 Color Palette Register 12 Color Palette Register 13 Color Palette Register 14 Color Palette Register 15 Mode Control Register Screen Border Color Color Plane Enable Register Pixel Panning Register Color Select Register (VGA)
D[4:0]
Preliminary V.10 Oct.07,1999
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Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset AR10: Mode Control Register Register Type: Read/Write Read Port: 3C1, Index 10h Write Port: 3C0, Index 10h Default: 00h D7 P4, P5 Source Select 0: AR0-F Bit[5:4] are used as the source for the Lookup Table Address Bit[5:4] 1: AR14 Bit[1:0] are used as the source for the Lookup Table Address Bit[5:4] D6 Pixel Double Clock Select 0: The pixels are clocked at every clock cycle 1: The pixels are clocked at every other clock cycle D5 PEL Panning Compatibility with Line Compare 0: Disable 1: Enable D4 Reserved D3 Background Intensity or Blink enable (while the Character Attribute D7=1) 0: Background Intensity attribute enable 1: Background Blink attribute enable D2 Line Graphics enable 0: The ninth bit of nine-bit-wide character cell will be the same as the background. 1: The ninth bit of nine-bit-wide character cell will be made be the same as the eighth bit for character codes in the range C0h through DFh. D1 Display Type 0: The contents of the Attribute byte are treated as color attribute. 1: The contents of the Attribute byte are treated as MDA-compatible attribute. D0 Graphics/Text Mode 0: The Attribute Controller will function in text mode. 1: The Attribute Controller will function in graphics mode. AR11: Screen Border Color Register Type: Read/Write Read Port: 3C1, Index 11h Write Port: 3C0, Index 11h Default: 00h D[7:6] Reserved D[5:0] Palette Entry
Preliminary V.10 Oct.07,1999
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Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset AR12: Color Plane Enable Register Register Type: Read/Write Read Port: 3C1, Index 12h Write Port: 3C0, Index 12h Default: 00h D[7:6] Reserved D[5:4] Display Status MUX Bit[1:0] These bits select two of the eight bits color outputs to be available in the status register. The output color combinations available on the status bits are as follows: Table 9.5-2 Table for Video Read-back Through Diagnostic Bit (I) Color Plane Enable Register D5 D4 0 0 1 0 1 0 Input Status Register 1 (Refer to 7.1.4) D5 D4 Red Secondary Red Secondary Blue Blue Secondary Green Green
1 1 Unused Unused Table 9.5-3 Table for Video Read-back Through Diagnostic Bit (II) Color Plane Enable Register D5 D4 0 0 1 1 D[3:0] 0 1 0 1 Enable Color Plane Bit[3:0] Input Status Register 1 (Refer to 7.1.4) D5 D4 P2 P5 P3 P7 P0 P4 P1 P6
AR13: Pixel Panning Register Register Type: Read/Write Read Port: 3C1, Index 13h Write Port: 3C0, Index 13h Default: 00h D[7:4] Reserved D[3:0] Pixel Pan Bit[3:0] This field specifies the number of pixels the display data will be shifted to the left. This field is interpreted as indicated in the following table: Table 9.5-4 Table of Pixel Panning D3 D2 D1 D0 Monochrome Text 162 VGA Mode 13 All Others
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8 0 1 2 3 4 5 6 7 Invalid Invalid Invalid Invalid Invalid Invalid Invalid 0 Invalid 1 Invalid 2 Invalid 3 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 0 1 2 3 4 5 6 7 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
AR14: Color Select Register Register Type: Read/Write Read Port: 3C1, Index 14h Write Port: 3C0, Index 14h Default: 00h D[7:4] Reserved D[3:2] Color Bit[7:6] These two bits are concatenated with the six bits from the Palette Register to form the address into the LUT and to drive P[7:6]. D[1:0] Color Bit[5:4] If AR10 D7 is programmed to a '1', these two bits replace the corresponding two bits from the Palette Register to form the address into the LUT and to drive P[5:4]. If AR10 D7 is programmed to a '0', these two bits are ignored.
9.6
Color Registers
DAC Status Register Register Type: Read Only Read Port: 3C7 Default: 00h D[7:2] Reserved Preliminary V.10 Oct.07,1999 163 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset D[1:0] DAC State Bit[1:0] 00: Write Operation in progress 11: Read Operation in progress
DAC Index Register (Read Mode) Register Type: Write Only Write Port: 3C7 Default: 00h D[7:0] DAC Index Bit[7:0] DAC Index Register (Write Mode) Register Type: Read/Write Read/Write Port: 3C8 Default: 00h D[7:0] DAC Index Bit[7:0] DAC Data Register Register Type: Read/Write Read/Write Port: 3C9 Default: 00h When SR7 D2 = 1 D[7:6] Reserved D[5:0] DAC Data [5:0] Before writing to this register, 3C8h is written with the DAC index. Then three values, corresponding to the Red, Green, and Blue values for the DAC entry are written. After the third value is written, the values are transferred to the LUT and the DAC index is incremented in case new values for the next DAC index are to be written. Before reading from this register, 3C7h is written with the DAC index. Then three values, corresponding to the Red, Green, and Blue value for the DAC entry may be read from this DAC index. After the third value is read, the DAC index is incremented in case the value for the next DAC index to be read. When SR7 D2 = 0 D[7:0] DAC Data [7:0] When SR7 D2 = 0, the 24-bit LUT is enabled. This LUT can translate the R, G, B values into new R, G, B values independently. This LUT can be used for performing GAMMA correction function. The programming procedure is same as standard LUT when SR7 D2 = 1. PEL Mask Register Register Type: Read/Write Read/Write Port: 3C6 Default: 00h D[7:0] Pixel Mask Bit[7:0] Preliminary V.10 Oct.07,1999 164 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset This field is the Pixel Mask for the palette DAC. If a bit in this field is programmed to '0', the corresponding bit in the pixel data will be ignored in looking up an entry in the LUT.
9.7
Extended Registers
Register Type: Read/Write Read/Write Port: 3C4 Default: 00h D[7:6] Reserved D[5:0] Extended Register Index Bit[5:0] (05h ~ 3Fh) Table 9.7-1 Table of Extended Registers Index (3C4) 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh Preliminary V.10 Oct.07,1999 Extended Enhanced Register (3C5) Extended Password/Identification Register Extended graphics mode register RAMDAC control register CRT threshold register I CRT threshold register II Extended vertical overflow register Extended horizontal overflow register I Extended horizontal overflow register II Extended CRT starting address register Extended CRT pitch register CRT misc. control register Display line width register DDC register Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 165 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh Preliminary V.10 Oct.07,1999 Reserved Segment Selection Overflow Register Module enable register Power management register GUI address decoder setting register GUI HostBus state machine setting register GUI HostBus controller timing register GUI HostBus timer register I Reserved Reserved Turbo Queue base address register Turbo Queue control register Reserved Reserved Reserved Extended DCLK clock generator register I Extended DCLK clock generator register II Extended DCLK clock generator register III Extended ECLK clock generator register I Extended ECLK clock generator register II Extended ECLK clock generator register III Extended clock generator misc. register Extended clock source selection register Reserved Interrupt status register Interrupt enable register Interrupt reset register Reserved Power on trapping register I Power on trapping register II Power on trapping register III Reserved Synchronous reset register Testing enabling register Reserved 166 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3Fh Reserved
9.8
VIDEO/TV Extended Registers
The following list is the registers of SIS630 relocate I/O: The index port of SIS630 video playback registers is RIO +02h. The data port of SiS 630 video playback registers is RIO +03h. The index port of SiS 630 digital video interface registers is RIO +04h. The data port of SiS 630 digital video interface registers is RIO +05h. The index port of SiS 301 TV encoder registers is RIO +10h. The data port of SiS 301 TV encoder registers is RIO +11h. The index port of SiS 301 macrovisontm registers is RIO +12h. The data port of SiS 301 macrovisontm registers is RIO +13h. The index port of SiS 301 VGA2 registers is RIO +0014h. The data port of SiS 301 VGA 2 registers is RIO +0015h. The SiS 301 palette address port register is RIO +0016h. The SiS 301 palette data port register is RIO +0017h. "RIO" is the configuration space base address register cnfg18 d[15:0] value.
Video Playback Index Register
Register Type: Read/Write Read/Write Port: RIO+02 Default: 00h D[7:0] Video playback register index Bit[7:0] (00h ~ 65h) Table 9.8-1 Table of Video Playback Registers Index (RIO+02) 00h 01h 02h 03h 04h 05h 06h 07h 08h Preliminary V.10 Oct.07,1999 Video Playback Register (RIO+03) Password/Identification Register Video Window Horizontal Display Start Low Register Video Window Horizontal Display End Low Register Video Window Horizontal Display Start/End High Register Video Window Vertical Display Start Low Register Video Window Vertical Display End Low Register Video Window Vertical Display Start/End High Register Video Display/Y Plane Frame Buffer Starting Address Low Register Video Display/Y Plane Frame Buffer Starting Address 167 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Middle Register 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h Preliminary V.10 Oct.07,1999 Video Display/Y Plane Frame Buffer Starting Address High Register Video U Plane Frame Buffer Starting Address Low Register Video U Plane Frame Buffer Starting Address Middle Register Video U Plane Frame Buffer Starting Address High Register Video V Plane Frame Buffer Starting Address Low Register Video V Plane Frame Buffer Starting Address Middle Register Video V Plane Frame Buffer Starting Address High Register Video Display/Y Plane Frame Buffer Pitch Low Register Video UV Plane Frame Buffer Pitch Low Register Video Display/Y Plane/UV Plane Frame Buffer Pitch High Register Video Display/Y Plane Frame Buffer Preset Low Register Video Display/Y Plane Frame Buffer Preset Middle Register Video UV Plane Frame Buffer Preset Low Register Video UV Plane Frame Buffer Preset Middle Register Video Display/Y Plane/UV Plane Frame Buffer Preset High Register Video Horizontal Post Scaling Factor Fraction Low Register Video Horizontal Post Scaling Factor Fraction High Register Video Vertical Scaling Factor Fraction Low Register Video Vertical Scaling Factor Fraction High Register Video Horizontal/Vertical Scaling Control Register Video Playback Threshold Low Value Register Video Playback Threshold High Value Register Video Playback Line Buffer Maximum Size Register Video Overlay Color Key Red Minimum Value Register Video Overlay Color Key Green Minimum Value Register Video Overlay Color Key Blue Minimum Value Register Video Overlay Color Key Red Maximum Value Register 168 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h Preliminary V.10 Oct.07,1999 Video Overlay Color Key Green Maximum Value Register Video Overlay Color Key Blue Maximum Value Register Video Chroma Key Red/Y Minimum Value Register Video Chroma Key Green/U Minimum Value Register Video Chroma Key Blue/V Minimum Value Register Video Chroma Key Red/Y Maximum Value Register Video Chroma Key Green/U Maximum Value Register Video Chroma Key Blue/V Maximum Value Register Video Contrast Enhancement Mean Value Sampling Rate Factor Register Video Brightness Value Register Video Contrast Enhancement Control Register Video Key Overlay Operation Mode Register Video Control Miscellaneous Register 0 Video Control Miscellaneous Register 1 Video Control Miscellaneous Register Register 2 Subpicture Frame Buffer Starting Address Low Register Subpicture Frame Buffer Starting Address Middle Register Subpicture Frame Buffer Starting Address/Preset High Register Subpicture Frame Buffer Preset Low Register Subpicture Frame Buffer Preset Middle Register Subpicture Frame Buffer Pitch Register Subpicture Horizontal Scaling Factor Fraction Low Register Subpicture Horizontal Scaling Factor Fraction High Register Subpicture Vertical Scaling Factor Fraction Low Register Subpicture Vertical Scaling Factor Fraction High Register Subpicture Horizontal/Vertical Scaling Factor Integer Register Subpicture Threshold Value Register Subpicture FIFO Maximum Size Register Subpicture Color Palette Color0 Low Register Subpicture Color Palette Color0 High Register Subpicture Color Palette Color1 Low Register 169 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h Subpicture Color Palette Color1 High Register Subpicture Color Palette Color2 Low Register Subpicture Color Palette Color2 High Register Subpicture Color Palette Color3 Low Register Subpicture Color Palette Color3 High Register Subpicture Color Palette Color4 Low Register Subpicture Color Palette Color4 High Register Subpicture Color Palette Color5 Low Register Subpicture Color Palette Color5 High Register Subpicture Color Palette Color6 Low Register Subpicture Color Palette Color6 High Register Subpicture Color Palette Color7 Low Register Subpicture Color Palette Color7 High Register Subpicture Color Palette Color8 Low Register Subpicture Color Palette Color8 High Register Subpicture Color Palette Color9 Low Register Subpicture Color Palette Color9 High Register Subpicture Color Palette ColorA Low Register Subpicture Color Palette ColorA High Register Subpicture Color Palette ColorB Low Register Subpicture Color Palette ColorB High Register Subpicture Color Palette ColorC Low Register Subpicture Color Palette ColorC High Register Subpicture Color Palette ColorD Low Register Subpicture Color Palette ColorD High Register Subpicture Color Palette ColorE Low Register Subpicture Color Palette ColorE High Register Subpicture Color Palette ColorF Low Register Subpicture Color Palette ColorF High Register MPEG Auto-Flipping Control Read-Back Register 0 MPEG Auto-Flipping Control Read-Back Register 1 MPEG Auto-Flipping Control Read-Back Register 2 MPEG Auto-Flipping Control Read-Back Register 3 MPEG Auto-Flipping Field Display Vertical Scaling Factor Fraction Low Register 170 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 65h MPEG Auto-Flipping Field Display Vertical Scaling Factor Fraction High Register
Digital Video Interface Register
Register Type: Read/Write Read/Write Port: RIO+04 Default: 00h D[5:0] Digital Video Interface Register Index Bit[7:0] (00h ~ 28h) Table 9.8-2 Table of digital video interface registers Index (RIO+04) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h Digital Video Interface Register (RIO+05) Function Control Register Mode Selection and FIFO Threshold High Mode Selection, PCI Bus Clock and FIFO Threshold Low FIFO Stop Operation Access Memory Starting Address High Access Memory Starting Address Median Access Memory Starting Address Low Access Memory Line Offset CRT2 Horizontal Total Overflow Register CRT2 Horizontal Display Enable End CRT2 Horizontal Retrace Start Overflow Register CRT2 Horizontal Retrace End CRT2 Vertical Total CRT2 Vertical Display Enable End CRT2 Vertical Retrace Start CRT2 Vertical Retrace End and Enable CRC Check and Overflow Register Hardware Cursor Test Mode and Overflow Register Software Command Reset, Panel Link Delay Compensation, Power Saving Panel Link Horizontal Retrace Start Panel Link Horizontal Retrace End/Skew Panel Link Horizontal Display Enable Start Panel Link Horizontal Display Enable End 171 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h Panel Link Vertical Retrace Start Panel Link Vertical Retrace End/Misc. Panel Link Control Signal and Vertical Retrace Start Panel Link Vertical Display Enable Start Panel Link Vertical Display Enable End Panel Link Control Signal / High Bits of Vertical Display Control Panel Link Vertical Scaling Factor Panel Link DDA Operational Number In Each Horizontal Line Overflow Register Panel Link Vertical Accumulator Length Panel Link Horizontal Scaling Factor High Panel Link Horizontal Scaling Factor Low CRT2 Enable Write Register CRT2 Vertical Retrace /Display Enable CRT2 Horizontal Counter Read Back CRT2 Vertical Counter Read Back CRT2 Horizontal Display Enable and Counter Overflow Read Back
9.9
PCI Configuration Registers
CNFG00: Configuration Register 00h Register Type: Read Read Port: 0000h Default: 03001039h D[31:16] Device ID SIS630 Device ID is 6300h D[15:0] Vendor ID SiS Vendor ID is 1039h CNFG04: Configuration Register 04h Register Type: Read/Write Read Port: 0004h Default: 02200004h D[26:25] DEVSEL* timing (= 01, Read Only) 00: fast 01: medium (fixed at this value) Preliminary V.10 Oct.07,1999 172 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 10: slow Fast back-to-back capable (=0 read only) 0: capable 1: not capable 66 MHz Capable 0: Support 33MHz 1: Support 66 MHz (fixed at this value) Capabilities List 0: does not implement a list of capabilities 1: implements a list of capabilities Fast back-to-back enable 0: disable 1: enable VGA Palette Snoop 0: Disable 1: Enable Bus Master 0: Device is not a bus master (fixed at this value) 1: Device is a bus master Memory Space 0: Disable 1: Enable I/O Space 0: Disable 1: Enable
D23
D21
D12
D9
D5
D3
D1
D0
CNFG08: Configuration Register 08h Register Type: Read Read Port: 0008h Default: 0300000Xh D[31:8] Class Code (= 030000h) D[7:0] Revision ID (= 0xh) CNFG10: Configuration Register 10h Register Type: Read/Write Read Port: 0010h Default: 00000008h D[31:0] 32-bit memory base register for 128MB linear frame buffer CNFG14: Configuration Register 14h Register Type: Read/Write Preliminary V.10 Oct.07,1999 173 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Read Port: Default: D[31:0] 0014h 00000000h 32-bit memory base register for 128KB memory mapped I/O
CNFG18: Configuration Register 18h Register Type: Read/Write Read Port: 0018h Default: 00000001h D[31:0] 32-bit I/O base register for 128 I/O space
CNFG2C: Configuration Register 2Ch Register Type: Read/Write Once Only Read Port: 002Ch Default: 00000000h D[31:16] Subsystem ID D[15:0] Subsystem Vendor ID CNFG30: Configuration Register 30h Register Type: Read/Write Read Port: 0030h Default: 000C0000h D[31:11] Expansion ROM Base Address D0 ROM Enable Bit 0: Disable 1: Enable CNFG3C: Configuration Register 3Ch Register Type: Read/Write Read Port: 003Ch Default: 00000100h D[15:8] Interrupt Pin (= 00h, Read Only) D[7:0] Interrupt Line (= 00h)
9.10
AGP Configuration Registers
Note: All the registers described in this section can be accessed only when AGP is enabled. CNFG34: Configuration Register 34h Register Type: Read Only Read Port: 0034h Default: 00000050h Preliminary V.10 Oct.07,1999 174 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset D[7:0] Capabilities list offset pointer (Read Only)
CNFG50: Configuration Register 50h Register Type: Read Only Read Port: 0050h Default: 00105c02h D[23:20] Major revision number D[19:16] Minor revision number D[15:8] Pointer to next item D[7:0] Cap_ID: value 02h identifies the list item as pertaining to AGP register CNFG54: Configuration Register 54h Register Type: Read Only Read Port: 0054h Default: 01000003h D[31:24] Maximum number of AGP command requests D9 Side band addressing support 0: Not support 1: Support D1 4X mode support 0: Not support 1: Support D1 2X mode support 0: Not support 1: Support D0 1X mode support 0: Not support 1: Support CNFG58: Configuration Register 58h Register Type: Read/Write Read Port: 0058h Default: 00000000h D[31:24] Maximum number of AGP requests can be enqueued D9 1: sideband address mode enable 0: sideband address mode disable D8 1: AGP enable 0: AGP disable D2 1: 4X mode enable 0: 4X mode disable D1 1: 2X mode enable Preliminary V.10 Oct.07,1999 175 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0: 2X mode disable 1: 1X mode enable 0: 1X mode disable
D0
CNFG5C: Configuration Register 5Ch Register Type: Read Read Port: 005Ch Default: 00000000h D[15:8] NULL: 00h indicates final item in the capability list
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10.1
Register Summary / Description -- Legacy
Register Summary
10.1.1 Legacy ISA Registers 10.1.1.1 DMA Registers Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 00C0h 00C2h 00C4h 00C6h 00C8h 00CAh 00CCh Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W WO WO WO R/W R/W R/W R/W R/W R/W R/W R/W Register Name DMA1 CH0 Base and Current Address Register DMA1 CH0 Base and Current Count Register DMA1 CH1 Base and Current Address Register DMA1 CH1 Base and Current Count Register DMA1 CH2 Base and Current Address Register DMA1 CH2 Base and Current Count Register DMA1 CH3 Base and Current Address Register DMA1 CH3 Base and Current Count Register DMA1 Status(r) Command(w) Register DMA1 Request Register DMA1 Command(r) Write Single Mask Bit (w) Register DMA1 Mode DMA Register DMA1 Clear Byte Pointer DMA1 Master Clear DMA1 Clear Mask Register DMA1 Write All Mask Bits(w) Mask Status(r) Register DMA2 CH0 Base and Current Address Register DMA2 CH0 Base and Current Count Register DMA2 CH1 Base and Current Address Register DMA2 CH1 Base and Current Count Register DMA2 CH2 Base and Current Address Register DMA2 CH2 Base and Current Count Register DMA2 CH3 Base and Current Address Register
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 00CEh 00D0h 00D2h 00D4h 00D6h 00D8h 00DAh 00DCh 00DEh R/W R/W R/W R/W R/W WO WO WO R/W DMA2 CH3 Base and Current Count Register DMA2 Status(r) Command(w) Register DMA2 Request Register DMA2 Command(r) Write Single Mask Bit(w) Register DMA2 Mode Register DMA2 Clear Byte Pointer DMA2 Master Clear DMA2 Clear Mask Register DMA2 Write All Mask Bits(w) Mask Status Register(r)
Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Register Name Reserved DMA Channel 2 Low Page Register DMA Channel 3 Low Page Register DMA Channel 1 Low Page Register Reserved Reserved Reserved DMA Channel 0 Low Page Register Reserved DMA Channel 6 Low Page Register DMA Channel 7 Low Page Register DMA Channel 5 Low Page Register Reserved Reserved Reserved Reserved
Address 00480h
Access R/W
Register Name Reserved 178 Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 00481h 00482h 00483h 00484h 00485h 00486h 00487h 00488h 00489h 0048Ah 0048Bh 0048Ch 0048Dh 0048Eh 0048Fh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DMA Channel 2 High Page Register DMA Channel 3 High Page Register DMA Channel 1 High Page Register Reserved Reserved Reserved DMA Channel 0 High Page Register Reserved DMA Channel 6 High Page Register DMA Channel 7 High Page Register DMA Channel 5 High Page Register Reserved Reserved Reserved Reserved
10.1.1.2 Interrupt Controller Registers Address 0020h 0021h 00A0h 00A1h Access R/W R/W R/W R/W INT 1 Mask Register INT 2 Base Address Register INT 2 Mask Register Register Name INT 1 Base Address Register
10.1.1.3 Timer Registers Address 0040h 0041h 0042h 0043h Access R/W R/W R/W WO Register Name Interval Timer 1 - Counter 0 Interval Timer 1 - Counter 1 Interval Timer 1 - Counter 2 Interval Timer 1 - Control Word Register
10.1.1.4 Other Registers Address Access 179 Register Name Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0061h 0070h 0092h 00F0h 04D0h 04D1h R/W WO R/W WO R/W R/W NMI Status Register CMOS RAM Address and NMI Mask Register INIT and A20 Register Coprocessor Error Register IRQ Edge/Level Control Register 1 IRQ Edge/Level Control Register 2
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11.1
Register Summary / Description - LPC Summary
LPC Bridge Configuration Registers
Access RO RO RO RO RO RO RO RO RO RO RO R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO R/W Register Name Vendor ID Device ID Command Register Status register Revision ID Class Code Cache Line Size Master Latency Timer Header Type Built-in Self Test Reserved BIOS Control Register PCI INTA#/B#/C#/D# Remapping Register Flash ROM Control Register INIT Enable Register Keyboard Controller Register RTC Control Register Individual Distributed DMA Channel Enable Register Distributed DMA Master Configuration Register Shadow Register of ICW1 to ICW4 of the INT1 Shadow Register of ICW1 to ICW4 of the INT2 Shadow Register of OCW 2&3 of INT1 Shadow Register of OCW 2&3 of the INT2 CTC Shadow Registers 1 to 8 Shadow Register for ISA Port 70 IDEIRQ Remapping Register 181 Silicon Integrated Systems Corporation
Address 00-01h 02-03h 04-05h 06-07h 08h 09-0Bh 0Ch 0Dh 0Eh 0Fh 10-3Ch 40h 41-44h 45h 46h 47h 48h 49h 4A-4Bh 4C-4Fh 50-53h 54-55h 56-57h 58h-5Fh 60h 61h
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 62h 63h 64h 65h 66h 67h 68-69h 6Ah 6Bh 6Ch 6Dh 6E-6Fh 70h 71-73h 74-75h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reserved. GPEIRQ Remapping Register Priority Timer PHOLD# Timer Reserved Clear SIRQ1 and SIRQ12 Reserved ACPI/SCI IRQ Remapping Register Reserved SMBUS IRQ Remapping Register Software Watchdog IRQ Remapping Register Software-Controlled Interrupt Requests Serial Interrupt Control Register Serial Interrupt Enable Register ACPI Base Address Register
11.2
LPC Bridge Configuration Registers
Device LPC Bridge IDSEL AD12 Function Number 0000b
Register 00h~01h Vendor ID Default Value: 1039h Access: Read Only Bit 15:0 Access RO Default value is 1039h Register 02h~03h Device ID Default Value: 0008h Access: Read Only Bit 15:0 Access RO Default value is 0008h Preliminary V.10 Oct.07,1999 182 Silicon Integrated Systems Corporation Description Device Identification Number Description Vendor Identification Number
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Note: Write a 1 to Reg40 bit 6 will change the Device ID to 0018h. Register 04h~05h Command Register Default Value: 000Ch Access: Read Only Bit 15:4 Access RO Reserved. Read as 0 3 2 1 RO RO RO Read as 1 to indicate that the device is allowed to monitor special cycles. Read as 1 to indicate that the device is able to become PCI bus master. Response to Memory Space Accesses (default=0) This bit is hardwired to1. 0 RO Response to Memory Space Accesses (default=0) This bit is hard wired to 1. Register 06h~07h Status Default Value: 0200h Access: Read Only Bit 15:14 13 Access RO RO Reserved. Read as 0 Received Master-Abort This bit will be set to 1 when the current transaction is terminated with master-abort. This bit can be cleared to 0 by writing a 1 to it. Received Target-Abort This bit will be set to 1 when the current transaction is terminated with target-abort. This bit can be cleared to 0 by writing a 1 to it. Reserved. Read as 0. DEVSEL# Timing The two bits are hardwired to 01 to indicate positive decode with medium timing. Description Description
12
RO
11 10:9
RO RO
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 8:0 RO Reserved. Read as 0.
Register 08h Revision ID Default Value: 00h Access: Read Only Bit 7:0 Access RO Description Revision Identification Number Default value is 00h indicating the A0 stepping.
Register 09h~0Bh Class Code Default Value: 060100h Access: Read Only Bit 23:0 Access RO Class Code Default value is 060100h. Register 0Ch Cache Line Size Default Value: 00h Access: Read Only Bit 7:0 Access RO Cache Line Size Description Description
Register 0Dh Master Latency Timer Default Value: 00h Access: Read Only Bit 7:0 Access RO Description Master Latency Timer
Register 0Eh Header Type Default Value: 80h Access: Read Only Bit 7:0 Access RO Header Type Default value is 80h Register 0Fh BIST 184 Silicon Integrated Systems Corporation Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Default Value: 00h Access: Read Only Bit 7:0 Access RO BIST Default value is 00h Register 10h~3Ch Reserved. Read as 0. Description
Register 40h BIOS Control Register Default Value: 00h Access: Read/Write Bit 7 Access R/W ACPI Enable 0 : Disable 1 : Enable When enabled, ACPI register at IO space address as defined in ACPI base registers (Reg 74h~75h) can be accessed. 6 R/W Device ID Selection 0 : LPC Bridge Device ID is 0008 1 : LPC Bridge Device ID is 0018 5 4 R/W R/W Reserved. PCI Posted Write Buffer Enable 0 : Disable (default) 1 : Enable 3 R/W Subtractive Decode to Internal registers Enable 0 : Disable 1 : Enable When this bit is enabled, SIS630 will do subtractive decode on addresses for internal registers. 2 R/W Reserved. Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1 R/W BIOS positive Decode Enable 0 : Disable 1 : Enable When enabled, SIS630 will positively respond to PCI memory cycles toward E segment and F segment. Otherwise, it will respond subtractively. 0 R/W Extended BIOS Enable. (FFF80000~FFFDFFFF) When enabled, SIS630 will positively respond to PCI cycles toward the Extended segment. Otherwise, it will have no response.
Register 41/42/43/44h PCI INTA#/B#/C#/D# Remapping Register Default Value: 80/80/80/80h Access: Read/Write Bit 7 Access R/W Remapping enable 0: Enable 1 : Disable When enabled, PCI INTA#/B#/C#/D# will be remapped to the IRQ channel specified below. 6:4 3:0 RO R/W Reserved. Read as 0 IRQ Remapping Table Bits 0000 0001 0010 0011 0100 0101 IRQx# reserved reserved reserved IRQ3 IRQ4 IRQ5 Bits 0110 0111 1000 1001 1010 1011 IRQx# IRQ6 IRQ7 Reserved IRQ9 IRQ10 IRQ11 Bits 1100 1101 1110 1111 IRQx# IRQ12 reserved IRQ14 IRQ15 Description
Note: More than one of INT[A:D]# can be remapped to the same IRQ line, but that IRQ line should be programmed to level-triggered mode. Table11.1-1 Interrupt Pin Reroute Table Function Interrupt Pin 186 Function Interrupt Pin
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Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset GUI AUDIO MODEM INTA INTB INTB MAC USB0 USB1 INTC INTD INTD
Register 45h Flash ROM Control Register Default Value: 40h Access: Read/Write Bit 7:6 Access R/W Description Flash EPROM Control Bit If bit 7 is set to '0' after CPURST de-asserted, EPROM can be flashed when bit 6 is set to '1'. Once bit 7 is set to '1', EPROM can not be flashed until the system is reset. Reserved.
5:0
R/W
Register 46h INIT Enable Register Default Value: 00h Access: Read/Write Bit 7:6 5 Access R/W R/W Description Hardware reset initiated by software When both set to 1, hardware reset will be generated to CPU. INIT Enable 0: Drives CPURST during S/W reset and INIT is inactive. 1 : Drives INIT during S/W reset 4 R/W Fast Gate 20 Emulation 0 : Disable 1 : Enable 3 R/W Fast Reset Latency Control 0 : 2us 1 : 6us 2 R/W Fast Reset Emulation 0 : Disable 1 : Enable
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1 R/W A20M# Output Control 0: Enable the assertion of A20M# if applicable. 1: Disable the assertion of A20M#, i.e., A20M# will be high at all times. 0 R/W Enable Keyboard Hardware Reset 0 : Disable 1 : Enable Note: Write a 1 to Port 92 bit 0 will cause SIS630 to drive INIT if INIT Enable bit is 1, and Port 92 bit 1 will be set to 1 concurrently to Disable the assertion of A20M#. Register 47h Keyboard Controller Register Default Value: 51h Access: Read/Write Bit 7 Access R/W Description USB Legacy Support Interface Enable 0 : Disable 1 : Enable 6 R/W PS/2 Mouse Lock Enable 0 : Disable 1 : Enable 5 R/W Internal Keyboard Controller Clock Selection 0 : PCICLK/4 1 : 7.159MHz 4 R/W Keyboard Lock Enable 0 : Disable 1 : Enable 3 R/W Integrated Keyboard Controller Enable 0 : Disable 1 : Enable 2 R/W Integrated PS/2 Mouse Enable 0 : Disable 1 : Enable This bit is meaningful only when Bit3 is enabled. Preliminary V.10 Oct.07,1999 188 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1 R/W Keyboard Hot Key Status This bit is set when hot key (Ctrl+Alt+Backspace) is pressed and should be cleared at the end of SMI# handler. This bit is meaningful only when internal KBC is enabled. 0 R/W Keyboard Hot Key Control 0 : Disable 1 : Enable This bit is meaningful only when internal KBC is enabled. Register 48h RTC Control Register Default Value: 10h Access: Read/Write Bit 7 Access R/W Description RTC Extended Bank Enable (EXTEND_EN) 0 : Disable 1 : Enable When this bit is enabled, the upper 128 bytes of RTC SRAM can be accessed. 6 R/W Automatic Power Control Registers (APCREG_EN) Enable 0 : Disable 1 : Enable When this bit is enabled, APC registers can be accessed. 5 R/W Instant Power-Off Enable (INSTOFF_EN) Before enabling this function, the bit1 at APC Register 04h should be enabled. System will be powered off if GPIO2_STS is set. Internal RTC Status 0 : Disable 1 : Enable 3:0 R/W Reserved.
4
RO
Register 49h Individual Distributed DMA Channel Enable Default Value: 00h Access: Read/Write Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W Channel 7 DDMA Enable Channel 6 DDMA Enable Channel 5 DDMA Enable Reserved. This bit must be programmed to 0. Channel 3 DDMA Enable Channel 2 DDMA Enable Channel 1 DDMA Enable Channel 0 DDMA Enable 0 : Disable 1 : Enable Register 4A~4Bh Distributed DMA Master Configuration Register Default Value: 0000h Access: Read/Write Bit 15:4 Access R/W Description DDMA slave base address bits[15:4] The DMA slave channels must be grouped into a 128 bytes block with 16 bytes per channel. The DMA slave channel 0 will be located at the base address specified here. Reserved. This bit must be programmed to 0. DDMA Function Enable 0 : Disable (default) 1 : Enable Register 4C~4Fh Shadow Register of ICW1 to ICW4 of INT1 Default Value: 00000000h Access: Read Only Bit 7:0 Access RO Description Reflect ICW1 to ICW4 of the master interrupt controller
3:1 0
R/W R/W
Register 50~53h Shadow Register of ICW1 to ICW4 of INT2 Default Value: 00000000h Access: Read Only Preliminary V.10 Oct.07,1999 190 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bit 7:0 Access RO Description Reflect ICW1 to ICW4 of the slave interrupt controller
Register 54~55h Shadow Register of OCW2 to OCW3 of INT1 Default Value: 0000h Access: Read Only Bit 7:0 Access RO Description Reflect OCW2 to OCW3 of the master interrupt controller
Register 54~55h Shadow Register of OCW2 to OCW3 of INT2 Default Value: 0000h Access: Read Only Bit 7:0 Access RO Description Reflect OCW2 to OCW3 of the slave interrupt controller
Register 58h CTC Shadow Register 1 Default Value: 00h Access: Read Only Bit 7:0 Access RO Description Reflect low byte of the initial count number of CTC Counter 0
Register 59h CTC Shadow Register 2 Default Value: 00h Access: Read Only Bit 7:0 Access RO Description Reflect high byte of the initial count number of CTC Counter 0
Register 5Ah CTC Shadow Register 3 Default Value: 00h Access: Read Only Bit 7:0 Access RO Description Reflect low byte of the initial count number of CTC Counter 1
Register 5Bh CTC Shadow Register 4 Default Value: 00h Access: Read Only Bit Access 191 Description Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:0 RO Reflect high byte of the initial count number of CTC Counter 1
Register 5Ch CTC Shadow Register 5 Default Value: 00h Access: Read Only Bit 7:0 Access RO Description Reflect low byte of the initial count number of CTC Counter 2
Register 5Dh CTC Shadow Register 6 Default Value: 00h Access: Read Only Bit 7:0 Access RO Description Reflect high byte of the initial count number of CTC Counter 2
Register 5Eh CTC Shadow Register 7 Default Value: 00h Access: Read Only Bit 7:0 Access RO Description Reflect Control word (43h) of the built-in CTC
Register 5Fh CTC Shadow Register 8 Default Value: 00h Access: Read Only Bit 7:6 5 Access RO RO Description Reserved. CTC counter2 Write count pointer status CTC counter1 Write count pointer status CTC counter0 Write count pointer status CTC counter2 Read count pointer status CTC counter1 Read count pointer status CTC counter0 Read count pointer status 0 : LSB 1 : MSB Register 60h Shadow Register for ISA port 70h 192 Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Default Value: FFh Access: Read Only Bit 7:0 Access RO Description Reflect the content of ISA port 70h register
Register 61h IDEIRQ Remapping Register Default Value: 80h Access: Read/Write Bit 7 Access R/W Description IDEIRQ Remapping Enable 0 : Enable 1 : Disable (default) 6:5 4 R/W R/W Reserved. IDE Channel Remapping Selection 0 : Primary IDE channel 1 : Secondary IDE channel 3:0 R/W IRQ Remapping Table Bits 0000 0001 0010 0011 0100 0101 IRQx# reserved reserved reserved IRQ3 IRQ4 IRQ5 Bits 0110 0111 1000 1001 1010 1011 IRQx# IRQ6 IRQ7 reserved IRQ9 IRQ10 IRQ11 Bits 1100 1101 1110 1111 IRQx# IRQ12 reserved IRQ14 IRQ15
Register 62h Reserved. Default Value: 80h Note: Bit 7 should be programmed to 1. Register 63h GPEIRQ Remapping Register Default Value: 80h Access: Read/Write Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7 R/W GPEIRQ Remapping Enable 0 : Enable 1 : Disable (default) 6:4 3:0 R/W R/W Reserved. IRQ Remapping Table Bits 0000 0001 0010 0011 0100 0101 Register 64h Priority Timer Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description Priority Timer There are four PCI maser candidates inside the south bridge competing for the PCI bus. They are LPC/DMA master, DDMA, PCI MASTER2 and PCI MASTER3 .The local arbiter with rotating scheme is adopted to coordinate their requests to become PCI master. The candidate that issues request to the arbiter with a higher priority is the winner and is eligible to become PCI master when PCI grant is received. The priority timer is used to set a lower limit in terms of PCI clock for the winning candidate to continue its PCI transactions. The timer will start counting as soon as the winning candidate receives the PCI grant. Upon expiration, the winning candidate' s priority will become lowest among the four and, if the requests issued by the other masters are outstanding, it will lose the ownership of PCI grant. The maximum allowable value is FFh and the minimum allowable value is 00h. Register 65h PHOLD# Timer Default Value: 01h Access: Read/Write Bit Access 194 Description Silicon Integrated Systems Corporation IRQx# reserved reserved reserved IRQ3 IRQ4 IRQ5 Bits 0110 0111 1000 1001 1010 1011 IRQx# IRQ6 IRQ7 reserved IRQ9 IRQ10 IRQ11 Bits 1100 1101 1110 1111 IRQx# IRQ12 reserved IRQ14 IRQ15
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:0 R/W PHOLD# Timer The PHOLD# timer sets an upper limit in terms of PCI clock for the assertion time of PHOLD# initiated by LPC/DMA Master, DDMA, PCI MASTER2 and PCI MASTER3. The timer starts and continues the counting when south bridge receives PCI grant. Upon expiration, the chip will be forced to de-assert PCI request to system arbiter . The maximum allowable value is FFh and the minimum allowable value is 01h. If a larger value is programmed, the master will be able to complete more PCI transactions by preventing the system arbiter from issuing grant to other PCI master candidates. The PCI bus bandwidth can be fairly shared by all PCI master candidates by properly program this timer. Register 66h Reserved. Read as 0.
Register 67h Clear SIRQ1 and SIRQ12 Default Value: 00h Access: Read/Write Bit 7 Access R/W Description ISR bits clear SIRQ1 and SIRQ 12 Latches Enable When set to 1, the internal latches for SIRQ1 and SIRQ12 will be cleared when the corresponding ISR bits are set in Interrupt Controller. The latches only take effective when either register 64h bit 7 or bit 6 is set to 1.The latches will always be cleared by a IO read cycle with address=60h. 6:5 R/W SMC37C673 Super I/O Compatible Mode These two bits should be programmed to 1 if a SMC37C673 Super IO chip is connected to SIS630 via serial IRQ line. Bit_6 enables the chipset to latch SIRQ1, while Bit_5 enables the chipset to latch SIRQ12. For all other super IO chips, the two bits should be programmed to 0 4 R/W Serial IRQ sampled IOCHK phase control 0: The sampled IOCHK on serial IRQ will be inverted. 1: The sampled IOCHK on serial IRQ will not be inverted. (Recommended) 3:0 Register 68h R/W Reserved.
Reserved. Read as 0.
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 69h Reserved. Read as 0.
Register 6Ah ACPI/SCI IRQ Remapping Register Default Value: 80h Access: Read/Write Bit 7 Access R/W Description ACPI/SCI IRQ Remapping Enable 0 : Enable 1 : Disable (default) 6:4 3:0 R/W R/W Reserved. IRQ Remapping Table Bits 0000 0001 0010 0011 0100 0101 Register 6Bh IRQx# reserved reserved reserved IRQ3 IRQ4 IRQ5 Bits 0110 0111 1000 1001 1010 1011 IRQx# IRQ6 IRQ7 reserved IRQ9 IRQ10 IRQ11 Bits 1100 1101 1110 1111 IRQx# IRQ12 reserved IRQ14 IRQ15
Reserved. Read as 0.
Register 6Ch SMBUS IRQ Remapping Register Default Value: 80h Access: Read/Write Bit 7 Access R/W Description SMBUS IRQ Remapping Enable 0 : Enable 1 : Disable (default) 6:5 4 3:0 R/W RO R/W Reserved. SMBus IRQ Status IRQ Remapping Table
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bits 0000 0001 0010 0011 0100 0101 IRQx# reserved reserved reserved IRQ3 IRQ4 IRQ5 Bits 0110 0111 1000 1001 1010 1011 IRQx# IRQ6 IRQ7 reserved IRQ9 IRQ10 IRQ11 Bits 1100 1101 1110 1111 IRQx# IRQ12 reserved IRQ14 IRQ15
Register 6Dh Software Watchdog IRQ Remapping Register Default Value: 80h Access: Read/Write Bit 7 Access R/W Description Software Watchdog IRQ Remapping Enable 0 : Enable 1 : Disable (default) 6:4 3:0 R/W R/W Reserved. IRQ Remapping Table Bits 0000 0001 0010 0011 0100 0101 IRQx# reserved reserved reserved IRQ3 IRQ4 IRQ5 Bits 0110 0111 1000 1001 1010 1011 IRQx# IRQ6 IRQ7 Reserved IRQ9 IRQ10 IRQ11 Bits 1100 1101 1110 1111 IRQx# IRQ12 reserved IRQ14 IRQ15
Register 6Eh Software-Controlled Interrupt Request, Channels 7-0 Default Value: 00h Access: Read/Write Bit 7 6 5 4 Access R/W R/W R/W R/W Interrupt Channel 7 Interrupt Channel 6 Interrupt Channel 5 Interrupt Channel 4 197 Silicon Integrated Systems Corporation Description
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3 2 1 0 R/W R/W R/W R/W Interrupt Channel 3 Interrupt Channel 2 Interrupt Channel 1 Interrupt Channel 0 Writing a 1 to these bits will cause the corresponding interrupt requests to be outstanding. The default value to all is 0. Register 6Fh Software-Controlled Interrupt Request, Channels 15-8 Default Value: 00h Access: Read/Write Bit 7 6 5 4 3 2 1 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Description Interrupt Channel 15 Interrupt Channel 14 Interrupt Channel 13 Interrupt Channel 12 Interrupt Channel 11 Interrupt Channel 10 Interrupt Channel 9 Interrupt Channel 8 Writing a 1 to these bits will cause the corresponding interrupt requests to be outstanding. The default value to all is 0. Register 70h Serial Interrupt Control Register Default Value: 00h Access: Read/Write Bit 7 Access R/W Description Serial Interrupt (SIRQ) Control 0 : Disable (default) 1 : Enable 6 R/W Quiet/Continuous Mode 0 : Continuous (default) 1 : Quiet
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5:2 R/W SIRQ Sample Period 0000: 17 slots (default) 0001: 18 slots 0010: 19 slots ::::::::::::: 1111: 32 slots 1:0 R/W Start Cycle length 00: 4 PCI clocks (default) 01: 6 PCI clocks 10: 8 PCI clocks 11: Reserved Register 71h Serial Interrupt Enable Register 1 Default Value: 00h Access: Read/Write Bit 7 6 5 4 3 2 1 Access R/W R/W R/W R/W R/W R/W R/W INV-SIRQ Serial SMI# Enable Serial IOCHCK# Enable Serial INTD Enable Serial INTC Enable Serial INTB Enable Serial INTA Enable 0 : Disable (default) 1 : Enable 0 R/W Reserved. Description
Register 72h Serial Interrupt Enable Register 2 Default Value: 00h Access: Read/Write Bit 7 6 Access R/W R/W Serial IRQ7 Enable Serial IRQ6 Enable 199 Silicon Integrated Systems Corporation Description
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W Serial IRQ5 Enable Serial IRQ4 Enable Serial IRQ3 Enable Reserved. Serial IRQ1 Enable Reserved. 0 : Disable (default) 1 : Enable Register 73h Serial Interrupt Enable Register 3 Default Value: 00h Access: Read/Write Bit 7 6 5 4 3 2 1 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Serial IRQ15 Enable Serial IRQ14 Enable Serial IRQ13 Enable Serial IRQ12 Enable Serial IRQ11 Enable Serial IRQ10 Enable Serial IRQ9 Enable Serial IRQ8 Enable 0 : Disable (default) 1 : Enable Register 74~75h ACPI BASE Register Default Value: 00h Access: Read/Write Bit 15:8 7:0 Access R/W RO Description ACPI Base Register A[15:8] ACPI registers will be located at the address specified here. Reserved. Read as 0. Description
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12
Register Summary / Description -USB Summary
There are two USB Host Controllers embedded in the SIS630 chipset. One is assigned as function2 and the other one is function3. Both of them are designed base on the Open Host Controller Interface Specification for USB Release 1.0a. The HostController of function2 supports a 3-port RootHub and the HostController of function3 supports a 2-port RootHub. Each of these two Host Controller contains a set of Configureation Space, Operational Registers and Legacy Support Registers.
12.1
USB OpenHCI Host Controller Configuration Space
12.1.1 USB Configuration Space Configuration. Offset 00-01h 02-03h 04-05h 06-07h 08h 09-0Bh 0Ch 0Dh 0Eh 0Fh 10-13h 13-3Bh 3Ch 3Dh 3Eh 3Fh Access RO RO R/W R/W RO RO RO R/W RO RO R/W RO R/W RO RO RO Mnemonic Register VID Vendor ID DID Device ID CMD Command Register STS Status register RID Revision ID CD Class Code CL Cache Line Size MLT Master Latency Timer HT Header Type BIST Built-in Self Test Base address Reserved INTL Interrupt line INTP Interrupt pin MINGNT Min Gnt MAXLAT Max Latency
12.2
USB OpenHCI Host Controller Operational Registers
The base address of these registers is programmable by the memory base address register (USB PCI configuration register offset 10-13h). These registers should be written as Dword. Bytes write to these registers have unpredictable effects. The OpenHCI Host Controller (HC) contains a set of on-chip operational registers that are mapped into a non-cacheable portion of the system addressable space. These registers are Preliminary V.10 Oct.07,1999 201 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset used by the Host Controller Driver (HCD). According to the functions of these registers, they are divided into four partitions, specifically for Control and Status, Memory Pointer, Frame Counter and Root Hub. All of the registers should be read and written as Dwords. Reserved bits may be allocated in future releases of this specification. To ensure interoperability, the Host Controller Driver that does not use a reserved field should not assume that the reserved field contains 0. Furthermore, the Host Controller Driver should always preserve the value(s) of the reserved field. When a R/W register is modified, the Host Controller Driver should first read the register, modify the bits desired, then write the register with the reserved bits still containing the read value. Alternatively, the Host Controller Driver can maintain an in-memory copy of previously written values that can be modified and then written to the Host Controller register. When a write to set/clear register is written, bits written to reserved fields should be 0. 12.2.1 Host Controller Operational Registers Offset 0 4 8 C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 3100 HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus[1] HcRhPortStatus[2] 202 Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5C 100 104 108 10C HcRhPortStatus[3] (Only for Function 2) HceControl HceInput HceOutput HceStatus
12.2.1.1 Control and Status Partition Register 00h HcRevision Register Default Value: 00000110h Access: Read Bit 31:9 8 RO Access Reserved Legacy This read-only field is 1 to indicate that the legacy support registers are present in this HC. Revision This read-only field contains the BCD representation of the version of the HCI specification that is implemented by this HC. For example, a value of 11h corresponds to version 1.1. All of the HC implementations that are compliant with current OpenHCI 1.0 specification will have a value of 10h. Description
7:0
RO
Register 04h HcControl Register Default Value: 00000000h Access: Read/Write The HcControl register defines the operating modes for the Host Controller. Only the Host Controller Driver, except Host Controller Functional State and Remote Wakeup Connected modifies most of the fields in this register. Bit 31:11 Access Reserved Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 10 R/O RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wakeup feature upon the detection of upstream resume signalling. When this bit is set and the Resume Detected bit in HC Interrupt Status is set, a remote wakeup is signalled to the host system. Setting this bit has no impact on the generation of hardware interrupt. Since there is no remote wakeup supported, this bit is ignored. 9 RO Remote Wakeup Connected This bit indicates whether HC supports remote wakeup signalling or not. If remote wakeup is supported and used by the system, it is the responsibility of system firmware to set this bit during POST. HC clears the bit upon a hardware reset but does not alter it upon software reset. Remote wakeup signalling of the host system is host-bus-specific and is not described in this specification. This bit is hard-coded to '0'. 8 R/W Interrupt Routing This bit determines the routing of interrupts generated by events registered in Hc Interrupt Status. If clear, all interrupts are routed to the normal host bus interrupt mechanism. If set, interrupts are routed to the System Management Interrupt. HCD clears this bit upon hardware reset, but it does not alter this bit upon a software reset. HCD uses this bit as a tag to indicate the ownership of HC. HostControllerFunctionalState for USB 00b: UsbReset 01b: UsbResume 10b: UsbOperational 11b: UsbSuspend A transition to UsbOperational from another state causes SOF generation to begin 1 ms later. HCD may determine whether HC has begun sending SOFs by reading the StartofFrame field of HcInterruptStatus. This field may be changed by HC only in the UsbSuspend state. HC may move from the UsbSuspend state to the UsbResume state after detecting the resume signal from a downstream port. HC enters UsbSuspend after a software reset, whereas it enters UsbReset after a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signal to downstream ports.
7:6
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5 R/W BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. If cleared by HCD, processing of the Bulk list does not occur after the next SOF. HC checks this bit whenever it determines to process the list. When disabled, HCD may modify the list. If HcBulkCurrentED is pointing to a ED to be removed, HCD must advance the pointer by updating HcBulkCurrentED before re-enabling the processing of the list. ControlListEnable This bit is set to enable the processing of the Control list in the next Frame. If cleared by HCD, the processing of the Control list does not occur after the next SOF. HC must check this bit whenever it determines to process the list. When disabled, HCD may modify the list. If HcControlCurrentED is pointing to a ED to be removed, HCD must advance the pointer by updating HcControlCurrentED before re-enabling the processing of the list. IsochronousEnable This bit is used by HCD to enable/disable the processing of isochronous EDs. While processing the periodic list in a Frame, HC checks the status of this bit when it finds an Isochronous ED (F=1). If set (enabled), HC continues processing the EDs. If cleared (disabled), HC halts processing of the periodic list (which now contains only isochronous EDs) and begins processing the Bulk/Control lists. Setting this bit is guaranteed to take effect in the next Frame (not the current Frame). PeriodicListEnable This bit is set to enable the processing of the periodic list in the next Frame. If cleared by HCD, the processing of the periodic list does not occur after the next SOF. HC must check this bit before it starts processing the list.
4
R/W
3
R/W
2
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1:0 R/W ControlBulkServiceRatio This specifies the service ratio between Control and Bulk EDs. Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many non-empty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs. The internal count will be retained when crossing the frame boundary. In case of reset, HCD is responsible for restoring this value. CBSR 0 1 2 3 No. of Control EDs Over Bulk EDs Served 1:1 2:1 3:1 4:1
Register 08h HcCommandStatus Register Default Value: 00000000h Access: Read/Write The HcCommandStatus register is used by the Host Controller to receive commands issued by the Host Controller Driver, as well as reflecting the current status of the Host Controller. To the Host Controller Driver, it appears to be a "write to set" register. The Host Controller must ensure those " written as '1'" bits become set in the register while those " written as ` 0'" bits remain unchanged in the register. The Host Controller Driver may issue multiple distinct commands to the Host Controller without concern for corrupting previously issued commands. The Host Controller Driver has normal read access to all bits. The SchedulingOverrunCount field indicates the number of frames with which the Host Controller has detected the scheduling overrun error. This occurs when the Periodic list does not complete before EOF. When a scheduling overrun error is detected, the Host Controller increments the counter and sets the SchedulingOverrun field in the HcInterruptStatus register. Bit 31:18 17:16 RO Access Reserved SchedulingOverrunCount These bits are incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be incremented when a scheduling overrun is detected even if Scheduling Overrun in Hc Interrupt Status has already been set. This is used by HCD to monitor any persistent scheduling problems. Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 15:4 3 R/W Reserved OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. When set HC will set the Ownership Change field in HcInterrupt Status. After the changeover, this bit is cleared and remains so until the next request from OS HCD. BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. It is set by HCD whenever it adds a TD to an ED in the Bulk list. When HC begins to process the head of the Bulk list, it checks BF. As long as BulkListFilled is 0, HC will not start processing the Bulk list. If BulkListFilled is 1, HC will start processing the Bulk list and will set BF to 0. If HC finds a TD on the list, then HC will set BulkListFilled to 1 causing the Bulk list processing to continue. If no TD is found on the Bulk list, and if HCD does not set BulkListFilled, then BulkListFilled will still be 0 when HC completes processing the Bulk list and Bulk list processing will stop. 1 R/W ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. It is set by HCD whenever it adds a TD to an ED in the Control list. When HC begins to process the head of the Control list, it checks CLF. As long as ControlListFilled is 0, HC will not start processing the Control list. If CF is 1, HC will start processing the Control list and will set ControlListFilled to 0. If HC finds a TD on the list, then HC will set ControlListFilled to 1 causing the Control list processing to continue. If no TD is found on the Control list, and if the HCD does not set ControlListFilled, then ControlListFilled will still be 0 when HC completes processing the Control list and Control list processing will stop 0 R/W HostControllerReset This bit is set by HCD to initiate a software reset of HC. Regardless of the functional state of HC, it moves to the UsbSuspend state in which most of the operational registers are reset except those stated otherwise; e.g., the InterruptRouting field of HcControl, and no Host bus accesses are allowed. This bit is cleared by HC upon the completion of the reset operation. The reset operation must be completed within 10 s. This bit, when set, should not cause a reset to the Root Hub and no subsequent reset signal should be asserted to its downstream ports. 207 Silicon Integrated Systems Corporation
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R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 0Ch HcInterruptStatus Register Default Value: 00000000h Access: Read/Write This register provides status on various events that cause hardware interrupts. When an event occurs, Host Controller sets the corresponding bit in this register. When a bit is set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register and the MasterInterruptEnable bit is set. The Host Controller Driver may clear specific bits in this register by writing '1'to bit positions to be cleared. The Host Controller Driver may not set any of these bits. The Host Controller will never clear the bit. Bit 31 30 R/W Access Reserved Ownership Change Status This bit is set by HC when HCD sets the Ownership Change Request field in HcCommandStatus. This event, when unmasked, will always generate an System Management Interrupt (SMI#) immediately. Reserved R/W RootHubStatusChange Status This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. FrameNumberOverflow Status This bit is set when the MSb of HcFmNumber (bit 15) changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. UnrecoverableError Status This bit is set when HC detects a system error not related to USB. HC should not proceed with any processing nor signaling before the system error has been corrected. HCD clears this bit after HC has been reset. This event is not implemented and is hard-coded to '0'. 3 R/W ResumeDetected Status This bit is set when HC detects that a device on the USB is asserting resume signaling. It is the transition from no resume signaling to resume signaling causing this bit to be set. This bit is not set when HCD sets the UsbResume state. StartofFrame Status This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. HC also generates a SOF token at the same time. 208 Silicon Integrated Systems Corporation Description
29:7 6
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1 R/W WritebackDoneHead Status This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not occur until this bit has been cleared. HCD should only clear this bit after it has saved the content of HccaDoneHead. SchedulingOverrun Status This bit is set when the USB schedule for the current Frame overruns and after the update of HccaFrameNumber. A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be incremented.
0
R/W
Register 10h HcInterruptEnable Register Default Value: 00000000h Access: Read/Write Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control those events generate a hardware interrupt. When a bit is set in the HcInterruptStatus register AND the corresponding bit in the HcInterruptEnable register is set AND the MasterInterruptEnable bit is set, then a hardware interrupt is requested on the host bus. Writing a '1' to a bit in this register sets the corresponding bit, whereas writing a '0' to a bit in this register leaves the corresponding bit unchanged. On read, the current value of this register is returned. Bit 31 Access R/W Description MasterInterrupt Enable A '0' written to this field is ignored by HC. A '1' written to this field enables interrupt generation due to events specified in the other bits of this register. This is used by HCD as a Master Interrupt Enable. OwnershipChange Enable 0 : Ignore 1 : Enable interrupt generation due to Ownership Change. 29:7 6 R/W Reserved RootHubStatusChange Enable 0 : Ignore 1 : Enable interrupt generation due to Root Hub Status Change. 5 R/W FrameNumberOverflow Enable 0 : Ignore 1 : Enable interrupt generation due to Frame Number Overflow. Preliminary V.10 Oct.07,1999 209 Silicon Integrated Systems Corporation
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R/W
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 4 3 R/W R/W UnrecoverableError Enable This event is not implemented. All writes to this bit will be ignored. ResumeDetected Enable 0 : Ignore 1 : Enable interrupt generation due to Resume Detect. 2 R/W StartofFrame Enable 0 : Ignore 1 : Enable interrupt generation due to Start of Frame. 1 R/W WritebackDoneHead Enable 0 : Ignore 1 : Enable interrupt generation due to HcDoneHead Writeback 0 R/W SchedulingOverrun Enable 0 : Ignore 1 : Enable interrupt generation due to Scheduling Overrun. Register 14h HcInterruptDisable Register Default Value: 00000000h Access: Read/Write Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register. Thus, writing a '1' to a bit in this register clears the corresponding bit in the HcInterruptEnable register, whereas writing a '0' to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On read, the current value of the HcInterruptEnable register is returned. Bit 31 Access R/W Description MasterInterrupt Disable A '0' written to this field is ignored by HC. A '1' written to this field disables interrupt generation due to events specified in the other bits of this register. This field is set after a hardware or software reset. OwnershipChange Disable 0 : Ignore 1 : Disable interrupt generation due to Ownership Change. 29:7 Reserved
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 6 R/W RootHubStatusChange Disable 0 : Ignore 1 : Disable interrupt generation due to Root Hub Status Change. 5 R/W FrameNumberOverflow Disable 0 : Ignore 1 : Disable interrupt generation due to Frame Number Overflow. 4 3 R/W R/W UnrecoverableError Disable This event is not implemented. All writes to this bit will be ignored. ResumeDetected Disable 0 : Ignore 1 : Disable interrupt generation due to Resume Detect. 2 R/W StartofFrame Disable 0 : Ignore 1 : Disable interrupt generation due to Start of Frame. 1 R/W WritebackDoneHead Disable 0 : Ignore 1 : Disable interrupt generation due to HcDoneHead Writeback. 0 R/W Scheduling Overrun Disable 0 : Ignore 1 : Disable interrupt generation due to Scheduling Overrun. 12.2.1.2 Memory Pointer Partition Register 18h HcHCCA Register Default Value: 00000000h Access: Read/Write The HcHCCA register contains the physical address of the Host Controller Communication Area. The Host Controller Driver determines the alignment restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA. The alignment is evaluated by examining the number of zeroes in the lower order bits. The minimum alignment is 256 bytes; therefore, bits 0 through 7 must always return '0' when read. This area is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the Host Controller Driver. Bit 31:8 Access R/W Description This is the base address of the Host Controller Communication Area. 211 Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:0 Reserved.
Register 1Ch HcPeriodCurrentED Register Default Value: 00000000h Access: Read/Write The HcPeriodCurrentED register contains the physical address of the current Isochronous or Interrupt Endpoint Descriptor. Bit 31:4 Access R/W Description PeriodCurrentED This is used by HC to point to the head of one of the Periodic lists that will be processed in the current Frame. The content of this register is updated by HC after a periodic ED has been processed. HCD may read the content in determining which ED is currently being processed at the time of reading. Reserved
3:0
Register 20h HcControlHeadED Register Default Value: 00000000h Access: Read/Write The HcControlHeadED register contains the physical address of the first Endpoint Descriptor of the Control list. Bit 31:4 Access R/W Description ControlHeadED HC traverses the Control list starting with the HcControlHeadED pointer. The content is loaded from HCCA during the initialization of HC. Reserved.
3:0
Register 24h HcControlCurrentED Register Default Value: 00000000h Access: Read/Write The HcControlCurrentED register contains the physical address of the current Endpoint Descriptor of the Control list. Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31:4 R/W ControlCurrentED This pointer is advanced to the next ED after serving the present one. HC will continue processing the list from where it left off in the last Frame. When it reaches the end of the Control list, HC checks the ControlListFilled in HcCommandStatus. If set, it copies the content of HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it does nothing. HCD is allowed to modify this register only when the ControlListEnable of HcControl is cleared. When set, HCD only reads the instantaneous value of this register. Initially, this is set to zero to indicate the end of the Control list. Reserved.
3:0
Register 28h HcBulkHeadED Register Default Value: 00000000h Access: Read/Write The HcBulkHeadED register contains the physical address of the first Endpoint Descriptor of the Bulk list. Bit 31:4 Access R/W Description BulkHeadED HC traverses the Bulk list starting with the HcBulkHeadED pointer. The content is loaded from HCCA during the initialization of HC. Reserved.
3:0
Register 2Ch HcBulkCurrentED Register Default Value: 00000000h Access: Read/Write The HcBulkCurrentED register contains the physical address of the current endpoint of the Bulk list. As the Bulk list will be served in a round-robin fashion, the endpoints will be ordered according to their insertion to the list. Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31:4 R/W BulkCurrentED This is advanced to the next ED after the HC has served the present one. HC continues processing the list from where it left off in the last Frame. When it reaches the end of the Bulk list, HC checks the ControlListFilled of HcControl. If set, it copies the content of HcBulkHeadED to HcBulkCurrentED and clears the bit. If it is not set, it does nothing. HCD is only allowed to modify this register when the BulkListEnable of HcControl is cleared. When set, the HCD only reads the instantaneous value of this register. This is initially set to zero to indicate the end of the Bulk list. Reserved.
3:0
Register 30h HcDoneHead Register Default Value: 00000000h Access: Read/Write The HcDoneHead register contains the physical address of the last completed Transfer Descriptor that was added to the Done queue. In normal operation, the Host Controller Driver should not need to read this register as its content is periodically written to the HCCA. Bit 31:4 Access R/W Description DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. HC then overwrites the content of HcDoneHead with the address of this TD. This is set to zero whenever HC writes the content of this register to HCCA. It also sets the WritebackDoneHead of HcInterruptStatus. 3:0 Reserved
12.2.1.3 Frame Counter Partition Register 34h HcFmInterval Register Default Value: 00002EDFh Access: Read/Write The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a Frame, (i.e., between two consecutive SOFs), and a 15-bit value indicating the Full Speed maximum packet size that the Host Controller may transmit or receive without causing scheduling overrun. The Host Controller Driver may carry out minor adjustment on the FrameInterval by writing a new value over the present one at each SOF. This provides the programmability necessary for the Host Controller to synchronize with an external clocking resource and to adjust any unknown local clock offset. Bit Access 214 Description Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31 R/W FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. FSLargestDataPacket This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. The counter value represents the largest amount of data in bits which can be sent or received by the HC in a single transaction at any given time without causing scheduling overrun. The field value is calculated by the HCD. Reserved R/W FrameInterval This specifies the interval between two consecutive SOFs in bit times. The nominal value is set to be 11,999. HCD should store the current value of this field before resetting HC. By setting the HostControllerReset field of HcCommandStatus as this will cause the HC to reset this field to its nominal value. HCD may choose to restore the stored value upon the completion of the Reset sequence. Register 38h HcFmRemaining Register Default Value: 00000000h Access: Read Only The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current Frame. Bit 31 Access RO Description FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. This bit is used by HCD for the synchronization between FrameInterval and FrameRemaining. Reserved RO FrameRemaining This counter is decremented at each bit time. When it reaches zero, it is reset by loading the FrameInterval value specified in HcFmInterval at the next bit time boundary. When entering the UsbOperational state, HC re-loads the content with the FrameInterval of HcFmInterval and uses the updated value from the next SOF. 215 Silicon Integrated Systems Corporation
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15:14 13:0
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 3Ch HcFmNumber Register Default Value: 00000000h Access: Read The HcFmNumber register is a 16-bit counter. It provides a timing reference among events occurring in the Host Controller and the Host Controller Driver. The Host Controller Driver may use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to the register. Bit 31:16 15:0 RO Access Reserved FrameNumber This is incremented when HcFmRemaining is re-loaded. It will be rolled over to 0h after ffffh. When entering the UsbOperational state, this will be incremented automatically. The content will be written to HCCA after HC has incremented the FrameNumber at each frame boundary and sent a SOF but before HC reads the first ED in that Frame. After writing to HCCA, HC will set the StartofFrame in HcInterruptStatus. Description
Register 40h HcPeriodicStart Register Default Value: 00000000h Access: Read/Write The HcPeriodicStart register has a 14-bit programmable value that determines when is the earliest time HC should start processing the periodic list. Bit 31:14 13:0 R/W Access Reserved PeriodicStart After a hardware reset, this field is cleared. This is then set by HCD during the HC initialization. The value is calculated roughly as 10% off from HcFmInterval. A typical value will be 3E67h. When HcFmRemaining reaches the value specified, processing of the periodic lists will have priority over Control/Bulk processing. HC will therefore start processing the Interrupt list after completing the current Control or Bulk transaction that is in progress. Description
Register 44h HcLSThreshold Register Default Value: 00000000h Access: Read/Write The HcLSThreshold register contains an 11-bit value used by the Host Controller to determine whether to commit to the transfer of a maximum of 8-byte LS packet before EOF. Neither the Host Controller nor the Host Controller Driver is allowed to change this value. Preliminary V.10 Oct.07,1999 216 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bit 31:12 11:0 Access Reserved R/W LSThreshold This field contains a value that is compared to the FrameRemaining field prior to initiating a Low Speed transaction. The transaction is started only if FrameRemaining this field. The value is calculated by HCD with the consideration of transmission and set-up overhead. Description
12.2.1.4 Root Hub Partition All registers included in this partition are dedicated to the USB Root Hub which is an integral part of the Host Controller though still a functionally separate entity. The HCD emulates USBD accesses to the Root Hub via a register interface. The HCD maintains many USB-defined hub features that are not required to be supported in hardware. For example, the Hub's Device, Configuration, Interface, and Endpoint Descriptors are maintained only in the HCD as well as some static fields of the Class Descriptor. The HCD also maintains and decodes the Root Hub's device address as well as other trivial operations that are better suited to software than hardware. The Root Hub register interface is otherwise developed to maintain similarity of bit organization and operation to typical hubs that are found in the system. Below are four register definitions: HcRhDescriptorA, HcRhDescriptorB, HcRhStatus, and HcRhPortStatus [5:1]. Each register is read and written as a Dword. These registers are only written during initialization to correspond with the system implementation. The HcRhDescriptorA and HcRhDescriptorB registers should be implemented such that they are writable regardless of the HC USB state. HcRhStatus and HcRhPortStatus must be writable during the USBOPERATIONAL state. Register 48h HcRhDescriptorA Register Default Value: 01000003h (function 2) / 01000002h (function3) Access: Read/Write The HcRhDescriptorA register is the first register of two describing characteristics of the Root Hub. Reset values are implementation-specific. The descriptor length (11), descriptor type (TBD), and hub controller current (0) fields of the hub Class Descriptor are emulated by the HCD. All other fields are located in the HcRhDescriptorA and HcRhDescriptorB registers. Bit 31:24 Access R/W Description PowerOnToPowerGoodTime This byte specifies the duration HCD has to wait before accessing a powered-on port of the Root Hub. It is implementation-specific. The unit of time is 2 ms. The duration is calculated as POTPGT * 2 ms. Reserved 217 Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 12 R/W NoOverCurrentProtection This bit describes how the overcurrent status for the Root Hub ports is reported. When this bit is cleared, the OverCurrentProtectionMode field specifies global or per-port reporting. 0 : Over-current status is reported collectively for all downstream ports 1 : No overcurrent protection supported 11 R/W OverCurrentProtectionMode This bit describes how the overcurrent status for the Root Hub ports is reported. At reset, this field should reflect the same mode as PowerSwitchingMode. This field is valid only if the NoOverCurrentProtection field is cleared. 0 : over-current status is reported collectively for all downstream ports 1 : over-current status is reported on a per-port basis 10 RO DeviceType This bit specifies that the Root Hub is not a compound device. The Root Hub is not permitted to be a compound device. This field should always read/write 0. NoPowerSwitching These bits are used to specify whether power switching is supported or ports are always powered. SIS630 USB HC supports global power switching mode. When this bit is cleared, the PowerSwitchingMode specifies global or per-port switching. 0 : Ports are power switched 1 : Ports are always powered on when the HC is powered on
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R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 8 R/W PowerSwitchingMode This bit is used to specify how the power switching of the Root Hub ports is controlled. SIS630 USB HC supports global power switching mode. This field is only valid if the NoPowerSwitching field is cleared. 0: all ports are powered at the same time. 1: Each port is powered individually. This mode allows port power to be controlled by either the global switch or per-port switching. If the PortPowerControlMask bit is set, the port responds only to port power commands (Set/ClearPortPower). If the port mask is cleared, then the port is controlled only by the global power switch (Set/ Clear Global Power). 7:0 RO NumberDownstreamPorts These bits specify the number of downstream ports supported by the Root Hub. One of the HC (function 2) supports three downstream ports, the other one (function 3) supports two downstream ports. Register 4Ch HcRhDescriptorB Register Default Value: 00000000h Access: Read/Write The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are written during initialization to configure the Root Hub. Bit 31:16 Access R/W Description PortPowerControlMask Each bit indicates if a port is affected by a global power control command when PowerSwitchingMode is set. When set, the port's power state is only affected by per-port power control (Set/ClearPortPower). When cleared, the port is controlled by the global power switch (Set/ClearGlobalPower). If the device is configured to global switching mode (PowerSwitchingMode=0), this field is not valid. SIS630 USB HC implements global power switching. bit 0: Reserved bit 1: Ganged-power mask on Port #1 bit 2: Ganged-power mask on Port #2 ... bit15: Ganged-power mask on Port #15 Preliminary V.10 Oct.07,1999 219 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 15:0 R/W DeviceRemovable Each bit is dedicated to a port of the Root Hub. When cleared, the attached device is removable. When set, the attached device is not removable. bit 0: Reserved bit 1: Device attached to Port #1 bit 2: Device attached to Port #2 ... bit15: Device attached to Port #15 Register 50h HcRhStatus Register Default Value: 00000000h Access: Read/Write The HcRhStatus register is divided into two parts. The lower word of a Dword represents the Hub Status field and the upper word represents the Hub Status Change field. Reserved bits should always be written '0'. Bit 31 Access WO Description ClearRemoteWakeupEnable(Write) Writing a '1' clears DeviceRemoveWakeupEnable. Writing a '0' has no effect. Reserved R/W OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. The HCD clears this bit by writing a '1'.Writing a ` 0 has no effect. ' LocalPowerStatusChange(Read) The Root Hub does not support the local power status feature; thus, this bit is always read as '0'. SetGlobalPower(Write) In global power mode (PowerSwitchingMode=0), This bit is written to '1' to turn on power to all ports (clear PortPowerStatus). In per-port power mode, it sets PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing a ` 0 has no effect. '
30:18 17
16
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 15 R/W DeviceRemoteWakeupEnable(Read) This bit enables a ConnectStatusChange bit as a resume event, causing a UsbSuspend to UsbResume state transition and setting the ResumeDetected interrupt. 0 : ConnectStatusChange is not a remote wakeup event. 1 : ConnectStatusChange is a remote wakeup event. SetRemoteWakeupEnable(Write) Writing a '1' sets DeviceRemoveWakeupEnable. Writing a '0' has no effect. 14:2 1 RO Reserved OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. When set, an overcurrent condition exists. When cleared, all power operations are normal. If per-port overcurrent protection is implemented this bit is always ` 0' LocalPowerStatus((Read)) The Root Hub does not support the local power status feature; thus, this bit is always read as '0'. ClearGlobalPower(Write) In global power mode (PowerSwitchingMode=0), This bit is written to '1' to turn off power to all ports (clear PortPowerStatus). In per-port power mode, it clears PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing a ` 0 has no ' effect. Register 54h/58h/5Ch HcRhPortStatus [3:1] Register Default Value: 00000000h Access: Read/Write The HcRhPortStatus[3:1] register is used to control and report port events on a per-port basis. Three or two HcRhPortStatus registers are implemented in each HC, respectively. The lower word is used to reflect the port status, whereas the upper word reflects the status change bits. Some status bits are implemented with special write behavior (see below). If a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completed. Reserved bits should always be written '0'. Bit 31:21 Access Reserved Description
0
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 20 R/W PortResetStatusChange This bit is set at the end of the 10-ms port reset signal. The HCD writes a '1' to clear this bit. Writing a '0' has no effect. 0 : port reset is not complete 1 : port reset is complete 19 R/W PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. This bit is set when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes a '1' to clear this bit. Writing a '0' has no effect. 0 : no change in PortOverCurrentIndicator 1 : PortOverCurrentIndicator has changed 18 R/W PortSuspendStatusChange This bit is set when the full resume sequence has been completed. This sequence includes the 20-s resume pulse, LS EOP, and 3ms resychronization delay. The HCD writes a '1' to clear this bit. Writing a '0' has no effect. This bit is also cleared when ResetStatusChange is set. 0 : resume is not completed 1 : resume completed 17 R/W PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. Changes from HCD writes do not set this bit. The HCD writes a '1' to clear this bit. Writing a '0' has no effect. 0 : no change in PortEnableStatus 1 : change in PortEnableStatus
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 16 R/W ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. The HCD writes a '1' to clear this bit. Writing a '0' has no effect. If CurrentConnectStatus is cleared when a SetPortReset, SetPortEnable, or SetPortSuspend write occurs, this bit is set to force the driver to re-evaluate the connection status since these writes should not occur if the port is disconnected. 0 : no change in CurrentConnectStatus 1 : change in CurrentConnectStatus Note: If the DeviceRemovable[NDP] bit is set, this bit is set only after a Root Hub reset to inform the system that the device is attached. 15:10 9 R/W Reserved LowSpeedDeviceAttached((Read)) This bit indicates the speed of the device attached to this port. When set, a Low Speed device is attached to this port. When clear, a Full Speed device is attached to this port. This field is valid only when the CurrentConnectStatus is set. 0 : full speed device attached 1 : low speed device attached
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 8 R/W Port Power Status((Read)) This bit reflects the port' s power status, regardless of the type of power switching implemented. This bit is cleared if an overcurrent condition is detected. HCD sets this bit by writing Set Port Power or Set Global Power. HCD clears this bit by writing Clear Port Power or Clear Global Power. Which power control switches will be enabled is determined by Power Switching Mode and Port Power Control Mask[NDP]. In global switching mode (Power Switching Mode=0), only Set/ClearGlobalPower controls this bit. In per-port power switching (Power Switching Mode=1), if the Port Power Control Mask[NDP] bit for the port is set, only Set/ClearPortPower commands are enabled. If the mask is not set, only Set/ Clear Global Power commands are enabled. When port power is disabled, Current Connect Status, Port Enable Status, Port Suspend Status, and Port Reset Status should be reset. 0 : port power is off 1 : port power is on SetPortPower(Write) The HCD writes a '1' to set the PortPowerStatus bit. Writing a '0' has no effect. Note: This bit is always reads ` 1b' if power switching is not supported. 7:5 4 R/W Reserved PortResetStatus(Read) When this bit is set by a write to SetPortReset, port reset signalling is asserted. When reset is completed, this bit is cleared when PortResetStatusChange is set. This bit cannot be set if CurrentConnectStatus is cleared. 0 : port reset signal is not active 1 : port reset signal is active SetPortReset(Write) The HCD sets the port reset signalling by writing a '1' to this bit. Writing a '0' has no effect. If CurrentConnectStatus is cleared, this write does not set PortResetStatus, but instead sets ConnectStatusChange. This informs the driver that it attempted to reset a disconnected port.
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3 R/W PortOverCurrentIndicator(Read) This bit is only valid when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. If per-port overcurrent reporting is not supported, this bit is set to 0. If cleared, all power operations are normal for this port. If set, an overcurrent condition exists on this port. This bit always reflects the overcurrent input signal 0 : no overcurrent condition. 1 : overcurrent condition detected. ClearSuspendStatus(Write) The HCD writes a '1' to initiate a resume. Writing a '0' has no effect. A resume is initiated only if PortSuspendStatus is set. 2 R/W PortSuspendStatus(Read) This bit indicates the port is suspended or in the resume sequence. It is set by a SetSuspendState write and cleared when PortSuspendStatusChange is set at the end of the resume interval. This bit cannot be set if CurrentConnectStatus is cleared. This bit is also cleared when PortResetStatusChange is set at the end of the port reset or when the HC is placed in the UsbResume state. If an upstream resume is in progress, it should propagate to the HC. 0 : port is not suspended 1 : port is suspended SetPortSuspend(Write) The HCD sets the PortSuspendStatus bit by writing a '1' to this bit. Writing a '0' has no effect. If CurrentConnectStatus is cleared, this write does not set PortSuspendStatus; instead it sets ConnectStatusChange. This informs the driver that it attempted to suspend a disconnected port.
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1 R/W PortEnableStatus(Read) This bit indicates whether the port is enabled or disabled. The Root Hub may clear this bit when an overcurrent condition, disconnect event, switched-off power, or operational bus error such as babble is detected. This change also causes PortEnabledStatusChange to be set. HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable. This bit cannot be set when CurrentConnectStatus is cleared. This bit is also set, if not already, at the completion of a port reset when ResetStatusChange is set or port suspend when SuspendStatusChange is set. 0 : port is disabled 1 : port is enabled SetPortEnable(Write) The HCD sets PortEnableStatus by writing a '1'.Writing a '0' has no effect. If CurrentConnectStatus is cleared, this write does not set PortEnableStatus, but instead sets ConnectStatusChange. This informs the driver that it attempted to enable a disconnected port. 0 R/W CurrentConnectStatus(Read) This bit reflects the current state of the downstream port. 0 : no device connected 1 : device connected ClearPortEnable(Write) The HCD writes a '1' to this bit to clear the PortEnableStatus bit. Writing a '0' has no effect. The CurrentConnectStatus is not affected by any write. Note: This bit is always read ` 1b' when the attached device is nonremovable (DeviceRemoveable[NDP]).
12.3
Legacy Support Registers
Four operational registers are used to provide the legacy support. Each of these registers is located on a 32-bit boundary. The offset of these registers is relative to the base address of the Host Controller operational registers with HceControl located at offset 100h. Table 12.3-1 Legacy Support Registers Offset 100h Register HceControl Description Used to enable and control the emulation hardware and report various status informations. 226 Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 104h 108h 10Ch HceInput HceOutput HceStatus Emulation side of the legacy Input Buffer register. Emulation side of the legacy Output Buffer register where keyboard and mouse data is to be written by software. Emulation side of the legacy Status register.
Three of the operational registers (HceStatus, HceInput, HceOutput) are accessible at I/O address 60h and 64h when emulation is enabled. Reads and writes to the registers using I/O addresses have side effects as outlined in the Table 12.3-2 Emulated Registers Table 12.3-2 Emulated Registers I/O Cycle Type Register Address Contents Side Effects Accessed/ Modified 60h IN HceOutput IN from port 60h will set OutputFull in HceStatus to 0 60h 64h 64h OUT IN OUT HceInput HceStatus HceInput OUT to port 60h will set InputFull to 1 and CmdData to 0 in HceStatus. IN from port 64h returns current value of HceStatus with no other side effect. OUT to port 64h will set InputFull to 0 and CmdData in HceStatus to 1.
Register 100h HceControl Register Default Value: 00000000h Access: Read/Write Bit 31:9 8 Access Reserved R/W A20State Indicates current state of Gate A20 on keyboard controller. Used to compare value to 60h when GateA20Sequence is active. IRQ12Active Indicates that a positive transition on IRQ12 from keyboard controller has occurred. SW may write a 1 to this bit to clear it (set it to 0). SW write of a 0 to this bit has no effect. IRQ1Active Indicates that a positive transition on IRQ1 from keyboard controller has occurred. SW may write a 1 to this bit to clear it (set it to 0). SW write of a 0 to this bit has no effect. 227 Silicon Integrated Systems Corporation Description
7
R/W
6
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5 R/W GateA20Sequence Set by HC when a data value of D1h is written to I/O port 64h. Cleared by HC on write to I/O port 64h of any value other than D1h. ExternalIRQEn When set to 1, IRQ1 and IRQ12 from the keyboard controller causes an emulation interrupt. The function controlled by this bit is independent of the setting of the EmulationEnable bit in this register. IRQEn When set, the HC generates IRQ1 or IRQ12 as long as the OutputFull bit in HceStatus is set to 1. If the AuxOutputFull bit of HceStatus is 0, then IRQ1 is generated; if it is 1, then an IRQ12 is generated. CharacterPending When set, an emulation interrupt is generated when the OutputFull bit of the HceStatus register is set to 0. EmulationInterrupt This bit is a static decode of the emulation interrupt condition EmulationEnable When set to 1, the HC is enabled for legacy emulation. The HC decodes accesses to I/O registers 60h and 64h and generates IRQ1 and/or IRQ12 when appropriate. Additionally, the HC generates an emulation interrupt at appropriate times to invoke the emulation software.
4
R/W
3
R/W
2
R/W
1 0
RO R/W
Register 104h HceInput Register Default Value: 00000000h Access: Read/Write Bit 31:8 Access Reserved Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:0 R/W InputData This register holds data that is written to I/O ports 60h and 64h. I/O data that is written to ports 60h and 64h is captured in this register when emulation is enabled. This register may be read or written directly by accessing it with its memory address in the Host Controller' s operational register space. When accessed directly with a memory cycle, reads and writes of this register have no side effects. Register 108h HceOutput Register Default Value: 00000000h Access: Read/write Bit 31:8 7:0 R/W Access Reserved OutputData This register hosts data that is returned when an I/O read of port 60h is performed by application software. The data placed in this register by the emulation software is returned when I/O port 60h is read and emulation is enabled. On a read of this location, the OutputFull bit in HceStatus is set to 0. Register 10Ch HceStatus Register Default Value: 00000000h Access: Read/Write Bit 31:8 7 6 5 Access Reserved R/W R/W R/W Parity Indicates parity error on keyboard/mouse data. Time-out Used to indicate a time-out AuxOutputFull IRQ12 is asserted whenever this bit is set to 1 and OutputFull is set to 1 and the IRQEn bit is set. Inhibit Switch This bit reflects the state of the keyboard inhibit switch and is set if the keyboard is NOT inhibited. Description Description
4
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3 R/W CmdData The HC sets this bit to 0 on an I/O write to port 60h and to 1 on an I/O write to port 64h Flag Nominally used as a system flag by software to indicate a warm or cold boot. InputFull Except for the case of a Gate A20 sequence, this bit is set to 1 on an I/O write to address 60h or 64h. While this bit is set to 1 and emulation is enabled, an emulation interrupt condition exists. OutputFull The HC sets this bit to 0 on a read of I/O port 60h. If IRQEn is set and AuxOutputFull is set to 0, then an IRQ1 is generated as long as this bit is set to 1. If IRQEn is set and AuxOutputFull is set to 1, then an IRQ12 is generated as long as this bit is set to 1. While this bit is 0 and CharacterPending in HceControl is set to 1, an emulation interrupt condition exists. The contents of the HceStatus Register are returned on an I/O Read of port 64h when emulation is enabled. Reads and writes of port 60h and writes to port 64h can cause changes in this register. Emulation software can directly access this register through its memory address in the Host Controller' s operational register space. Accessing this register through its memory address produces no side effects.
2
R/W
1
R/W
0
R/W
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13
13.1
Register Summary / Description - Fast Ethernet / Home Networking Summary
MAC and PHY Registers
13.1.1 MAC Configuration Space (Function 1) Configuration. Offset 00-01h 02-03h 04-05h 06-07h 08h 09-0Bh 0Ch 0Dh 0Eh 0Fh 10-13h 14-17h 18-28h 2C-2Fh 30-33h 34-37h 38-3Bh 3C-3Fh 40-43h 44-47h 48-FFh Access RO RO R/W R/W RO RO RO R/W RO RO R/W R/W RO R/W R/W R/W RO R/W R/W R/W RO Mnemonic Register Vendor ID Device ID Command Register Status Register Revision ID Class Code Cache Line Size Master Latency Timer Header Type Built-in Self Test Configuration IO Base Address Register Configuration Memory Address Register RESERVED (reads return zero) Configuration Register Subsystem Identification
Configuration Expansion ROM Base Address Register Configuration Capabilities Pointer Register RESERVED (reads return zero). Configuration Interrupt Select Register Configuration Power Capabilities Register Management
Configuration Power Management Control and Status Register RESERVED (reads return zero)
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 13.1.2 MAC Operational Registers Configuration. Offset 00-03h 04-07h 08-0Bh 0C-0Fh 10-13h 14-17h 18-1Bh 1C-1Fh 20-23h 24-27h 28-2Fh 30-33h 34-37h 38-3Bh 3C-47h 48-4Bh 4C-4Fh 50-AFh B0-B3h B4-B7h B8-BBh BC-BFh C0-EFh F0-FFh Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W R/W RO R/W R/W R/W R/W R/W R/W Mnemonic Register Command Register Configuration Register EEPROM Access Register PCI Test Control Register Interrupt Status Register Interrupt Mask Register Interrupt Enable Register Enhanced PHY Access Register Transmit Descriptor Pointer Register Transmit Configuration Register RESERVED Receive Descriptor Pointer Register Receive Configuration Register Flow Control Register RESERVED Receive Filter Control Register Receive Filter Data Register RESERVED Power Management Control Register Power Management Wake-up Event Register RESERVED Wake-up Sample Frame CRC Register Wake-up Sample Frame Mask Registers RESERVED
13.1.3 PHY Configuration Registers Configuration. Offset 00h 01h Preliminary V.10 Oct.07,1999 Access R/W R/W 232 Mnemonic Register MI Register 0 Control Register MI Register 1 Status Register Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 02h 03h 04h 05h 10h 11h 12h 13h 14h R/W R/W R/W R/W R/W R/W R/W R/W R/W MI Register 2 PHY ID#1 MI Register 3 PHY ID#2 MI Register 4 Auto Negotiation Advertisement MI Register 5 Auto Negotiation Remote End Capability MI Register 16 Configuration 1 MI Register 17 Configuration 2 MI Register 18 Status Output MI Register 19 Mask MI Register 20 Reserved
13.2
10M/100M Ethernet Controller Registers
The SiS Ethernet Controller is configured and controlled through registers. There are three categories of control/status registers implemented inside the SiS Ethernet Controller, which includes PCI Configuration Registers, MAC Operational Registers and MII PHY Registers. The PCI Configuration registers are mapped into PCI configuration space and accessed using PCI configuration bus cycles. The MAC Operational registers can be mapped into either PCI memory or PCI IO space. MII PHY Registers are accessed through MAC Operational Register ENPHY (Enhanced PHY access register, offset 1Ch). The SiS Ethernet Controller requires an allocation of 256 bytes of operational register space, and 72 bytes of PCI configuration register space. The detailed definitions for each bit allocated in each register will be described in section 4.2, 4.3 and 4.4 respectively. Acronyms mentioned in the PCI configuration registers and MAC Operational registers are defined as follows: RO Read Only R/W Read Write Acronyms mentioned in the MII PHY registers that are defined as follows: Sym. W R R/W R/WSC Write Read Read/Write Read/Write Cleaning Name Write Cycle Input No Operation Input Self Input Definition Read Cycle No Operation Output Output Output Clears itself After Operation Complete 233 Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset R/LL Read/Latching Low No Operation Output When Bit Goes Low, Bit Latched. When Bit is Read, Bit Updated. Output When Bit Goes High, Bit Latched. When Bit is Read, Bit Updated. Output When Bit Transitions, Bit Latched And Interrupt Set When Bit is Read, Interrupt Clear And Bit Updated.
R/LH
Read/Latching High
No Operation
R/LT
Read/Latching Transition
on No Operation
13.3
PCI Configuration Registers
The SiS Ethernet Controller implements a PCI version 2.1 configuration register space. This allows PCI BIOS to "soft" configure the SiS Ethernet Controller. Software Reset has no effect on configuration registers. Hardware Reset returns all configuration registers to their hardware reset state. For all reserved registers, a write are ignored, and a read return 0. Table 13.3-1 Configuration Register Map Offset 00h 04h 08h 0Ch 10h 14h 18h-28h 2Ch 30h CFGSID CFGEROMA Tag CFGID CFGCS CFGRID CFGLAT CFGIOA CFGMA Description Configuration Identification Register Configuration Command and Status Register Configuration Revision ID Register Configuration Revision ID Register Configuration Register Configuration Register IO Base Address Address Access RO R/W RO R/W R/W R/W Section 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6
Memory
RESERVED (reads return zero). Configuration Identification Register Subsystem RO R/W 4.2.7 4.2.8
Configuration Expansion ROM Base 234
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Address Register 34h 38h 3Ch 40h 44h 48-FFh CFGINT CFGPMC CFGPMCSR CFGCAP Configuration Register Capabilities Pointer RO 4.2.9
RESERVED (reads return zero). Configuration Register Interrupt Select R/W RO R/W 4.2.10 4.2.11 4.2.12
Configuration Power Capabilities Register
Management
Configuration Power Management Control and Status Register RESERVED (reads return zero).
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Register 00h Configuration Identification Default Value: 09001039h Access: Read Only This register identifies The SiS Ethernet Controller to PCI system software. Bit 31:16 Access RO Description Device ID This field is read-only and is set to the device ID 0900h assigned by SiS if auto load is not enabled. If auto load is enabled, it is set to the device ID stored in Serial EEPROM. Vendor ID This field is read-only and is set to a value of 1039h that is SiS' s PCI Vendor ID if auto load is not enabled. If auto load is enabled, it is set to the vendor ID stored in EEPROM.
15:0
RO
Register 04h Configuration Command and Status Default Value: 02900000h Access: Read/Write This register has two parts. The upper 16-bits (31-16) is devoted to device status. The lower 16-bits (15-0) is devoted to command and are used to configure and control the device. Bit 31 Access R/W Description Detected Parity Error The SiS Ethernet Controller sets this bit whenever a parity error is detected, even if the parity error handling is disabled (controlled by command register bit 6). SW writes ` 1' to this bit will clear this bit. SW writes ` 0 to this bit leaves this bit unchanged. ' Signalled SERR This bit is set whenever the SiS Ethernet Controller asserts SERR#. SW writes ` 1' to this bit will clear this bit. SW writes ` 0' to this bit leaves this bit unchanged. Received Master Abort The SiS Ethernet Controller sets this bit whenever its master transaction is terminated with Master-Abort. SW writes ` 0' to this bit leaves this bit unchanged. Received Target Abort The SiS Ethernet Controller sets this bit whenever its master transaction is terminated with Target-Abort. SW writes ` 0 to this bit ' leaves this bit unchanged.
30
R/W
29
R/W
28
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 27 R/W Sent Target Abort The SiS Ethernet Controller sets this bit whenever it terminates a target transaction with Target-Abort. SW writes ` 0' to this bit leaves this bit unchanged. DEVSEL Timing This field will always be set to 01 indicating that the SiS Ethernet Controller supports " medium" DEVSEL timing. Data Parity Detected This bit is set when three conditions are met: (1) the bus agent asserted PERR# itself or observed PERR# asserted; (2) The SiS Ethernet Controller acted as the bus master for the operation in which the error occurred; and (3) the Parity Error Response bit in command register is set. SW writes ` 0 to this bit leaves this bit ' unchanged. Fast Back-to-Back Capable The SiS Ethernet Controller will set this bit to 1. User Definable Features Supported The SiS Ethernet Controller does not support User Definable Features, and therefore reads will return a 0. 66MHz Capable The SiS Ethernet Controller is not 66MHz capable. Reads will return a 0. Capabilities The SiS Ethernet Controller will set this bit to 1 indicating implementation of extended capabilities (PCI power management). Reserved Reads return 0. R/W Fast Back-to-Back Enable Set to 1 by the PCI BIOS to enable the SiS Ethernet Controller to do Fast Back-to-Back transfers (FBB transfers as a master is not implemented in the current revision). SERR# Enable When set, the SiS Ethernet Controller will generate SERR# when an address parity error is detected.
26:25
RO
24
R/W
23 22
RO RO
21
RO
20
RO
19:10 9
8
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7 RO Address Data Stepping This bit is hardwired to 0 for the SiS Ethernet Controller never do stepping. Parity Error Response When set, The SiS Ethernet Controller will assert PERR# on the detection of a data parity error when acting as the target, and will sample PERR# when acting as the initiator. When reset, data parity errors are ignored. The action taken is specified by CFG: PESEL. VGA Palette Snoop The SiS Ethernet Controller does not implement this bit. Reads will return a 0. Memory Write and Invalidate Enable Set to 0 indicating that The SiS Ethernet Controller will not generate the Memory Write and Invalidate command. Special Cycles Set to 0 indicating that The SiS Ethernet Controller will ignore all Special Cycle operations. Bus Master Enable When set, The SiS Ethernet Controller is allowed to act as a PCI bus master. When reset, The SiS Ethernet Controller is prohibited from acting as a PCI bus master. Memory Space Access When set, The SiS Ethernet Controller responds to memory space accesses. When reset, The SiS Ethernet Controller ignores memory space accesses. IO Space Access When set, The SiS Ethernet Controller responds to IO space accesses. When reset, The SiS Ethernet Controller ignores IO space accesses.
6
R/W
5
RO
4
RO
3
RO
2
R/W
1
R/W
0
R/W
Register 08h Configuration Revision ID Default Value: 02000080h Access: Read Only This register stores silicon revision number, revision number of software interface specification and lets the configuration software know that it is an Ethernet controller in the class of network controllers. Bit Access 238 Description Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31:24 RO Base Class Returns 02 which specifies a network controller. 23:16 RO Sub Class Returns 00, which specifies an Ethernet controller. 15:8 RO Programming IF Returns 00, which specifies the first release of The SiS Ethernet Controller Software Interface Specification. 7:0 RO Silicon Revision Returns 80, which specifies the silicon revision. Register 0Ch Configuration Latency Timer Default Value: 00000000h Access: Read/Write This register gives status and controls such miscellaneous functions as BIST, Latency timer and Cache line size. Bit 31:24 Access RO Description Built-in Self Test The SiS Ethernet Controller do not support BIST. Read will return 0, write is ignored. Header Type 00h Latency Timer Set by software to the number of PCI clocks that The SiS Ethernet Controller may hold the PCI bus. Cache Line Size Ignored by The SiS Ethernet Controller.
23:16 15:8
RO R/W
7:0
RO
Register 10h Configuration IO Base Address Default Value: 00000001h Access: Read/Write This register specifies the Base I/O address that is required to build an address map during configuration. It also specifies the number of bytes required as well as an indication that it can be mapped into I/O space. Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31:8 R/W Base IO Address This is set by software to the base IO address for the Operational Register Map. Size indication Read back as 0. This allows the PCI bridge to determine that The SiS Ethernet Controller requires 256 bytes of IO space. Reserved Reads return 0. RO IO Space Indicator Set to 1 by The SiS Ethernet Controller to indicate that The SiS Ethernet Controller is capable of being mapped into IO space.
7:2
RO
1 0
Register 14h Configuration Memory Address Default Value: 00000000h Access: Read/Write This register specifies the Base Memory address that is required to build an address map during configuration. It also specifies the number of bytes required as well as an indication that it can be mapped into memory space. Bit 31:12 Access R/W Description Memory Base Address This is set by software to the base address for the Operational Register Map. Memory Size These bits return 0, which indicates that The SiS Ethernet Controller requires 4096 bytes of Memory Space (the minimum recommended allocation) Prefetchable Set to 0 by The SiS Ethernet Controller to indicate that The SiS Ethernet Controller does not support this feature. Location Selection Set to 00 by The SiS Ethernet Controller. This indicates that the base register is 32-bits wide and can be placed anywhere in the 32-bit memory space Memory Space Indicator Set to 0 by The SiS Ethernet Controller to indicate that The SiS Ethernet Controller is capable of being mapped into memory space.
11:4
RO
3
RO
2:1
RO
0
RO
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 2Ch Configuration Subsystem Identification Default Value: 09001039h Access: Read Only This register allows system software to distinguish between different subsystems based on the same PCI silicon. Bit 31:16 Access RO Description Subsystem Device ID This field is set to the device ID 0900h assigned by SiS if auto load is not enabled. If auto load is enabled, it is set to the subsystem ID stored in EEPROM. Subsystem Vendor ID This field is set to a value of 1039h, which is SiS' s PCI Vendor ID if auto load is not enabled. If auto load is enabled, it is set to the subvendor ID stored in EEPROM.
15:0
RO
Register 30h Configuration Expansion ROM Base Address Default Value: 00000000h Access: Read/Write This register specifies the Base Expansion ROM address that is required to build an address map during configuration. It also specifies the number of bytes required as well as an indication that the device accepts accesses to its expansion ROM. Bit 31:17 Access R/W Description Expansion ROM Base Address This is set by software to the base address for the Expansion ROM. Reserved Reads return 0. R/W Expansion ROM address decode enable This The SiS Ethernet Controller will respond to access its expansion ROM when this bit is set and the Memory Space Access bit is set.
16:1 0
Register 34h Configuration Capabilities Pointer Default Value: 00000040h Access: Read Only Bit 31:8 Access Reserved Reads return 0. 241 Silicon Integrated Systems Corporation Description
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:0 RO Capabilities Pointer It provides an offset into PCI configuration space for the location of the first item in the capabilities linked list. Hardwired to 40' h in The SiS Ethernet Controller to point to CFGPMC.
Register 3Ch Configuration Interrupt Select Default Value: 0b340300h Access: Read/Write This register stores the interrupt line number as identified by the POST software that is connected to the interrupt controller as well as The SiS Ethernet Controller desired settings for maximum latency and minimum grant. Bit 31:24 Access RO Description Maximum Latency The SiS Ethernet Controller desired setting for Max Latency. The SiS Ethernet Controller will initialize this field to 0B (2.75 sec). Minimum Grant The SiS Ethernet Controller desired setting for Minimum Grant. The SiS Ethernet Controller will initialize this field to 34 (13 sec). Interrupt Pin Always return 0000 0011 (INTC). Interrupt Line Set to which line on the interrupt controller that The SiS Ethernet Controller' s interrupt pin is connected to.
23:16
RO
15:8 7:0
RO R/W
Register 40h Configuration Power Management Capabilities Default Value: fe010001h Access: Read Only The SiS Ethernet Controller supports both PCI Bus Power Management Interface specifications. revision 1.0 and revision 1.0a. If auto load is enabled, the CFGPMC register is 1.0a version, otherwise it is 1.0 version. 1.0 version: Bit 31:27 Access RO Description PME Support Indicates PME# may be asserted from which power state. If Auxiliary Power Source is present, this 5-bit field is 11111b indicating PME# can be asserted from D0, D1, D2, D3hot and D3cold. If Auxiliary Power Source is absent, this 5-bit field is 01111b indicating PME# can be asserted from D0, D1, D2 and D3hot but cannot be asserted from D3cold. 242 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 26 RO D2 Support Set to 1 by The SiS Ethernet Controller to indicate that The SiS Ethernet Controller supports D2 Power Management State. D1 Support Set to 1 by The SiS Ethernet Controller to indicate that The SiS Ethernet Controller supports D1 Power Management State. Reserved Reads return 0. RO Device Specific Initialization Set to 0 by The SiS Ethernet Controller to indicate that The SiS Ethernet Controller does not require a device specific initialization sequence following transition to the D0 uninitialized state. Reserved Reads return 0. RO PME Clock Set to 0 by The SiS Ethernet Controller to indicate that no PCI clock is required for The SiS Ethernet Controller to generate PME#. PCI PM Spec. Version Set to 001b indicates that The SiS Ethernet Controller complies with Revision 1.0 of the PCI Power Management Interface Specification. Next Item Pointer Set to 00h by The SiS Ethernet Controller to indicate that no additional items in the Capabilities List. Capability ID Set to 01h by The SiS Ethernet Controller to indicate that the linked list item as being the PCI Power Management registers.
25
RO
24:22 21
20 19
18:16
RO
15:8
RO
7:0
RO
1.0a version: Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31:27 RO PME Support Indicates PME# may be asserted from which power state. If Auxiliary Power Source is present, this 5-bit field is 11111b indicating PME# can be asserted from D0, D1, D2, D3hot and D3cold. If Auxiliary Power Source is absent, this 5-bit field is 01111b indicating PME# can be asserted from D0, D1, D2 and D3hot but cannot be asserted from D3cold. D2 Support Set to 1 by The SiS Ethernet Controller to indicate that The SiS Ethernet Controller supports D2 Power Management State. D1 Support Set to 1 by The SiS Ethernet Controller to indicate that The SiS Ethernet Controller supports D1 Power Management State. Auxiliary Current This field reports the 3.3Vaux auxiliary current requirements for The SiS Ethernet Controller. Device Specific Initialization Set to 0 by The SiS Ethernet Controller to indicate that The SiS Ethernet Controller does not require a device specific initialization sequence following transition to the D0 uninitialized state. Reserved Reads return 0. RO PME Clock Set to 0 by The SiS Ethernet Controller to indicate that no PCI clock is required for The SiS Ethernet Controller to generate PME#. PCI PM Spec. Version Set to 010b indicates that The SiS Ethernet Controller complies with Revision 1.0a of the PCI Power Management Interface Specification. Next Item Pointer Set to 00h by The SiS Ethernet Controller to indicate that no additional items in the Capabilities List. Capability ID Set to 01h by The SiS Ethernet Controller to indicate that the linked list item as being the PCI Power Management registers.
26
RO
25
RO
24:22
RO
21
RO
20 19
18:16
RO
15:8
RO
7:0
RO
Register 44h
Configuration Power Management Control/Status 244 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Default Value: 00000000h Access: Read/Write This register is used to manage The SiS Ethernet Controller' s power management state as well as to enable/monitor PME Bit 31:24 23:16 15 Access RO RO R/W Description State Dependent Data Not implemented in The SiS Ethernet Controller (reads return 0). PMCSR PCI to PCI Bridge Support Extensions Not implemented in The SiS Ethernet Controller (reads return 0). PME Status This bit is set when The SiS Ethernet Controller would normally assert the PME# signal independent of the state of the PME_EN bit. Writing a ` 1 to this bit will clear it and cause The SiS Ethernet ' Controller to stop asserting a PME# (if enabled). Writing a ` 0 has ' no effect. If Auxiliary Power Source is present, i.e. PME# can be asserted from D3cold, then this bit must be explicitly cleared by the operating system each time the operating system is initially loaded. Unchanged by hardware reset. Data Scale Not implemented in The SiS Ethernet Controller (reads return 0). Data Select Not implemented in The SiS Ethernet Controller (reads return 0). PME Enable Writing a ` 1 enables The SiS Ethernet Controller to assert PME#. ' Writing a ` 0 , PME# assertion is disabled. If Auxiliary Power ' Source is present, i.e. PME# can be asserted from D3cold, then this bit must be explicitly cleared by the operating system each time the operating system is initially loaded. Unchanged by hardware reset. Reserved Reads return 0
14:13 12:9 8
RO RO R/W
7:2
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1:0 R/W Power State This 2-bit field is used both to determine the current power state of The SiS Ethernet Controller and to set The SiS Ethernet Controller into a new power state. The hardware reset value is 00b. The definition of the field values is given below. 00b 01b 10b 11b D0 D1 D2 D3hot
13.4
MAC Operational Registers
The SiS Ethernet Controller provides the following set of operational registers mapped into PCI memory space or I/O space. Writes to reserved register locations may result in unexpected behavior. Reads to reserved register locations will return unspecified value. Table 13.4-1 Operational Register Map Register 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28-2Ch 30h 34h 38h 3C-44h 48h RFCR RXDP RXCFG FLOWCTL CR CFG EROMAR PTSCR ISR IMR IER ENPHY TXDP TXCFG Tag Description Command Register Configuration Register EEPROM Access Register PCI Test Control Register Interrupt Status Register Interrupt Mask Register Interrupt Enable Register Enhanced PHY Access Register Transmit Register Descriptor Pointer Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Section 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10
Transmit Configuration Register RESERVED Receive Register Descriptor Pointer
R/W R/W R/W
4.3.11 4.3.12 4.3.13
Receive Configuration Register Flow Control Register RESERVED Receive Filter Control Register 246
R/W
4.3.14
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 4Ch 50-ACh B0h B4h B8h BCh C0-ECh F0-FCh WAKECRC WAKEMASK PMCTL PMEVT RFDR Receive Filter Data Register RESERVED Power Management Register Power Management Event Register RESERVED Wake-up Register Sample Frame CRC R/W R/W 4.3.18 4.3.19 Control Wake-up R/W R/W 4.3.16 4.3.17 R/W 4.3.15
Wake-up Sample Frame Mask Registers RESERVED
Register 00h Command Default Value: 00000000h Access: Read/Write This register is used for issuing commands to The SiS Ethernet Controller. These commands are issued by setting the corresponding bits for the function. Global software reset along with individual reset and enable/disable switches for transmitter and receiver are provided here. Bit 31-10 9 8 Access Reserved R/W R/W HomePHY Software Reset Set to 1 to reset HomePHY and set to 0 to clear reset. Reset Set to 1 to force The SiS Ethernet Controller to a soft reset state, which disables the transmitter and receiver, reinitializes the FIFOs, and resets all affected registers to their soft reset state. This operation implies both a TXR and a RXR. This bit will read back a 1 during the reset operation, and be cleared to 0 by the hardware when the reset operation is complete. Software Interrupt Setting this bit to a 1 forces The SiS Ethernet Controller to generate a hardware interrupt. This interrupt is maskable via the IMR. Reserved Description
7
R/W
6
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5 R/W Receiver Reset When set to a 1, this bit causes the current packet reception to be aborted, the receiver data and status FIFOs to be flushed, and the receiver state machine to enter the idle state (RXE goes to 0). This is a write-only bit and is always read back as 0. Transmit Reset When set to a 1, this bit causes the current transmission to be aborted, the transmitter data and status FIFOs to be flushed, and the transmitter state machine to enter the idle state (TXE goes to 0). This is a write-only bit and is always read back as 0. Receiver Disable Disable the receiver' s state machine after any current packets in progress. When this operation has been completed the RXE bit will be cleared to 0. This is a write-only bit and is always read back as 0. If the programmer is silly enough to set both RXD and RXE in the same write, the RXE will be ignored, and RXD will have precedence. Receiver Enable When set to a 1, and the receiver' s state machine is idle, then the receiver' s machine becomes active. This bit will read back as a 1 whenever the receive state machine is active. After initial powerup, software must insure that the receiver has completely reset before setting this bit (see ISR:RXRCMP) Transmit Disable When set to a 1, halts the transmitter after the completion of the current packet. This is a write-only bit and is always read back as 0. If the programmer is silly enough to set both TXD and TXE in the same write, the TXE will be ignored, and TXD will have precedence. Transmit Enable When set to a 1, and the transmit state machine is idle, then the transmit state machine becomes active. This bit will read back as a 1 whenever the transmit state machine is active. After initial power-up, software must insure that the transmitter has completely reset before setting this bit (see ISR:TXRCMP)
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
Register 04h Configuration Default Value: 00000000h Access: Read/Write Bit Access 248 Description Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31-8 7 R/W Reserved PCI Bus Request Algorithm Selects mode for making requests for the PCI bus. When set to 0 (default), The SiS Ethernet Controller will use an aggressive Request scheme. When set to a 1, The SiS Ethernet Controller will use a more conservative scheme. Single Backoff Setting this bit to 1 forces the transmitter backoff state machine to always backoff for a single 802.3 slot time instead of following the 802.3 random backoff algorithm. 0 (default) allows normal transmitter backoff operation. Program Out of Window Timer This bit controls when the Out of Window collision timer begins counting its 512-bit slot time. A 0 causes the timer to start after the SFD is received. A 1 causes the timer to start after the first bit of the preamble is received. R/W Excessive Deferral Timer disable Setting this bit to 1 will inhibit transmit errors due to excessive deferral. This will inhibit the setting of the ED status. Parity Error Detection Action This bit control the assertion of SERR when a data parity error is detected while The SiS Ethernet Controller is acting as the bus master. When set, parity errors will not result in the assertion of SERR. When reset, parity errors will result in the assertion of SERR, indicating a system error. Reserved R/W Big Endian Mode When set, The SiS Ethernet Controller will perform bus-mastered data transfers in " big endian" mode. Note that access to register space is unaffected by the setting of this bit.
6
R/W
5
4
3
R/W
2-1 0
Register 08h Serial EEPROM Access Default Value: 00000000h Access: Read/Write Bit 31-8 Access Reserved Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7 R/W HomePHY Register Access Set to 1 to access HomePHY registers and set to 0 to access EEPROM. Reserved R/W EEPROM Chip Select / HomePHY Register Select In EEPROM chip select mode, it controls the value of the EECS pin. When set, the EECS pin is 1; when clear the EECS pin is 0. In HomePHY register select mode, set to 0 to enable access. 2 R/W EEPROM Serial Clock / HomePHY Register Serial Clock In EEPROM chip select mode, it controls the value of the EESK pin. When set, the EESK pin is 1; when clear the EESK pin is 0. In HomePHY register select mode, when set, serial clock is 1; when clear, serial clock is 0. 1 RO EEPROM Data Out / HomePHY Register Data Out In EEPROM chip select mode, it returns the current state of the EEDO/PA2 pin when EECS is 1. When EECS is 0, this bit returns 0. In HomePHY register select mode, it returns the data of HomePHY register. 0 R/W EEPROM Data In / HomePHY Register Data In In EEPROM chip select mode, it controls the value of the EEDI pin. In HomePHY register select mode, HomePHY register. Register 08h PCI Test Control Default Value: 34000000h Access: Read/Write Bit 31 30 R/W Access Reserved Discard Timer Test Mode Setting this bit to 1, the discard timer for delay transaction will have an initial value of 3ff0h. Setting this bit to 0, the initial value of the discard timer will be 0 and the counter expires when up-count to 3fffh. Default value is set to 0. Description it controls the data input of
6-4 3
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Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 29-28 27-24 R/W Reserved Boot ROM Access Time This field adjusts the boot ROM access time. The default value is 0100b that equal to 4 PCI clocks. Reserved R/W TX/RX RAM address Used as the address for the Transmit/Receive data FIFO when accessed through TXCFG/RXCFG during RAM test mode. Reserved R/W Bus Master Test Enable When enabled (set to 1), the bus master test mode allows the TX buffer manager to be used as a bus master read cycle generator, and the RX buffer manager to be used as a bus master write cycle generator. While in this test mode, normal buffer manager operation is inhibited. The BMTEN bit should only be set to 1 after the TX and RX have been reset and disabled. After setting BMTEN to 0, the TX and RX must be reset and reconfigured to allow normal operation to resume. Reserved R/W Receive RAM Test Mode Enable Set this bit to 1 to enable Receive RAM Test mode, which will allow read/write access to the RX data FIFO. The address is specified in bit20-12 RAM address field. The data is written to or read from the RXCFG register. Transmit RAM Test Mode Enable Set this bit to 1 to enable Transmit RAM Test mode, which will allow read/write access to the TX data FIFO. The address is specified in bit20-12 RAM address field. The data is written to or read from the TXCFG register. Status RAM Test Mode Enable Set this bit to 1 to enable Status RAM Test mode, which will allow read/write access to the RX status FIFO. The address is specified in bit4-0 Status RAM address field. The data is written to or read from the RXCFG register. Status RAM address Used as the address for the receiver status FIFO when accessed through RXCFG during RAM test mode.
23-21 20-12
11-10 9
8 7
6
R/W
5
R/W
4-0
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bus Master Read Cycle Test Mode Generation When the BMTEN bit is set to 1, the TX buffer manager will generate bus master read cycles on command. Several of the TX operational register bit fields are redefined to facilitate control of this mode. TXDP Read cycle starting address (dword aligned only).
TXCFG:DRTH Length of read cycle in bytes (1-335 bytes). The actual length value is derived as follows: length[8:0] = {DRTH[5], 0, DRTH[4], 0, 0, DRTH[3:0]}. NOTE: TXCFG:MXDMA is still utilized while in this test mode to control the maximum DMA size. It is recommended that TXCFG:MXDMA be set to 0 so that the byte count in TXCFG:DRTH will control the DMA length. CR:TXE Write a "1" to this bit will invoke the read cycle.
The sequence required to generate bus master read cycle is as follows: Write a 1 to CR:TXR (not necessary if this mode is invoked immediately after reset) Write a 1 to PTSCR:BMTEN Write a Dword aligned starting address to the TXDP reg WRITE A BYTE LENGTH TO THE TXCFG:DRTH Write a 1 to the CR:TXE All data read during this bus master cycle is discarded (bit bucket). Read cycles can be initiated repetitively without resetting TX between cycles. TXDP, and TXCFG data are retained between cycles. Bus Master Write Cycle Test Mode Generation When the BMTEN bit is set to 1, the RX buffer manager will generate bus master write cycles on command. Several of the RX operational register bit fields are redefined to facilitate control of this mode. RXDP Write cycle starting address (Dword aligned only).
RXCFG:DRTH Length of write cycle in bytes (1-335 bytes). The actual length value is derived as follows: length[8:0] = {DRTH[5], 0, DRTH[4], 0, 0, DRTH[3:0]}. NOTE: RXCFG:MXDMA is still utilized while in this test mode to control the maximum DMA size. It is recommended that RXCFG:MXDMA be set to 0 so that the byte count in the RXCFG:DRTH bits will control the DMA length. RXstatus[22:0] Write cycle data (this data byte value is used for all byte lanes - see below for data pattern) CR:RXE Writing a "1" to this bit will invoke the write cycle
Data from the Receive status FIFO is used to provide the bus data for the write cycles. A location in the RX status FIFO must be written and read using RAM test mode to initialize the desired data pattern. The status data mapping used for each byte lane (little endian) during the Preliminary V.10 Oct.07,1999 252 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset generated write cycles is as follows: byte 0 : status[7:0] byte 1 : status[15:8] byte 2 : {status[0], status[22:16]} byte 3 : status[8:1] The sequence required to generate bus master write cycle is as follows: Write a 1 to CR:RXR (not necessary if this mode is invoked immediately after reset) Write a 1 to PTSCR:SRTMEN and 00000 to PTSCR:SRAMADR[4:0] Write desired data pattern to RXCFG (Note: Only bits 22-0 are used) Read RXCFG Write a 1 to PTSCR:BMTEN Write a dword aligned starting address to the RXDP register Write a byte length to the RXCFG:DRTH Write a 1 to the CR:RXE Write cycles can be initiated repetitively without resetting RX between cycles. RXDP, RX status, and RXCFG data are retained between cycles. The sequence from step 1 to step 4 also describes the status RAM test mode procedure, as a example with address 00000. Similarly, Transmit and Receive RAM test mode can be achieved as follows: 1. Write a 1 to CR:TXR (not necessary if this mode is invoked immediately after reset) 2. Write a 1 to PTSCR:TRTMEN and the address to PTSCR:TRRAMADR[20:12] 3. Write desired data pattern to TXCFG 4. Read RXCFG Register 10h Interrupt Status Default Value: 03008000h Access: Read Only This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one or more bits in this register are set to a " 1". The Interrupt Status Register reflects all current pending interrupts, regardless of the state of the corresponding mask bit in the IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect. Bit 31-29 Access Reserved Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 28 RO Wake Up Event Indicates that there is wake-up event occurs. This bit is a wired version of PM Event registers bits, it' s not a registered one. So this bit will not be cleared by read operation like others status bits do, it is read as ` 0' when all PM Event registers bits are cleared. End of Transmission Pause Indicates pause command is completed when pause timer expires. Start of Transmission Pause Indicates data transmission is paused. Transmit Reset Complete Indicates that a requested transmit reset operation is complete. Receive Reset Complete Indicates that a requested receive reset operation is complete. Detected Parity Error This bit is set whenever CFGCS:DPERR is set, but cleared (like all other ISR bits) when the ISR register is read. Signaled System Error The SiS Ethernet Controller signaled a system error on the PCI bus. Received Master Abort The SiS Ethernet Controller received a master abort on the PCI bus. Received Target Abort The SiS Ethernet Controller received a target abort on the PCI bus. Reserved RO RO RX Status FIFO Overrun Set when an overrun condition occurs on the RX Status FIFO. High Bits Error Set A logical OR of bits 25-16 Reserved RO Software Interrupt Set whenever the SWI bit in the CR register is set. Reserved 254 Silicon Integrated Systems Corporation
27
RO
26 25 24 23
RO RO RO RO
22
RO
21
RO
20
RO
19-17 16 15 14-13 12 11
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 10 9 RO RO TX Underrun Set when a transmit data FIFO underrun condition occurs. TX Idle This event is signaled when the transmit state machine enters the idle state from a non-idle state. This will happen whenever the state machine encounters an "end-of-list" condition (NULL link field or a descriptor with OWN clear). TX Packet Error This event is signaled after the last transmit descriptor in a failed transmission attempt that has been updated with valid status. TX Descriptor This event is signaled after a transmitter descriptor with the INTR bit set in the CMDSTS field that has been updated. TX Packet OK This event is signaled after the last transmit descriptor in a successful transmission attempt has been updated with valid status RX Overrun Set when a receive data FIFO overrun condition occurs. RX Idle This event is signaled when the receive state machine enters the idle state from a running state. This will happen whenever the state machine encounters an "end-of-list" condition (NULL link field or a descriptor with OWN set). RX Early Threshold Indicates that the initial RX Drain Threshold has been met by the incoming packet, and the transfer of the number of bytes specified by the DRTH field in the RXCFG register has been completed by the receive DMA engine. This interrupt condition will occur only once per packet. RX Packet Error This event is signaled after the last receive descriptor in a failed packet reception that has been updated with valid status. RX Descriptor This event is signaled after a receiver descriptor with the INTR bit set in the CMDSTS field that has been updated.
8
RO
7
RO
6
RO
5 4
RO RO
3
RO
2
RO
1
RO
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 RO RX OK Set by the receive state machine following the update of the last receive descriptor in a good packet.
Register 14h Interrupt Mask Default Value: 00000000h Access: Read/Write This register masks the interrupts that can be generated from the ISR. Writing a "1" to the bit enables the corresponding interrupt. During hardware reset, all mask bits are cleared. Bit 31-29 28 R/W Access Reserved Wake Up Event When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. End of Transmission Pause When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. Start of Transmission Pause When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. Transmit Reset Complete When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. Receive Reset Complete When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. Detected Parity Error When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. Signaled System Error When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. Received Master Abort When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. Description
27
R/W
26
R/W
25
R/W
24
R/W
23
R/W
22
R/W
21
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 20 R/W Received Target Abort When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. Reserved R/W R/W RX Status FIFO Overrun Set when an overrun condition occurs on the RX Status FIFO. High Bits Error Set When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. Reserved R/W Software Interrupt When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. Reserved R/W TX Underrun When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. TX Idle When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. TX Packet Error When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. TX Descriptor When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. TX Packet OK When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. RX Overrun When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. RX Idle When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 257 Silicon Integrated Systems Corporation
19-17 16 15
14-13 12
11 10
9
R/W
8
R/W
7
R/W
6
R/W
5
R/W
4
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3 R/W RX Early Threshold When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. RX Packet Error When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. RX Descriptor When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. RX OK When this bit is 0, the corresponding bit in the ISR will not cause an interrupt.
2
R/W
1
R/W
0
R/W
The Interrupt Mask Register provides a mechanism for enabling individual interrupt sources in the Interrupt Status Register (ISR). Setting a mask bit allows the corresponding bit in the ISR to cause an interrupt. ISR bits are always set to 1, however, if the condition is present, regardless of the state of the corresponding mask bit. Register 18h Interrupt Enable Default Value: 00000000h Access: Read/Write The Interrupt Enable Register controls the hardware INTR signal. Bit 31-1 0 Access Reserved R/W Interrupt Enable When set to 1, the hardware INTR signal is enabled. When set to 0, the hardware INTR signal will be masked, and no interrupts will be generated. The setting of this bit has no effect on the ISR or IMR. This provides the ability to disable the hardware interrupt to the host with a single access (eliminating the need for a readmodify-write cycle). Description
Register 1Ch Enhanced PHY Access Default Value: 00000000h Access: Read/Write The SiS Ethernet Controller provides ten internal MII PHY registers for internal PHY configuration settings and status readings. Driver can access the ten internal MII registers by defining the command, Register offset, desired data from the ENPHY resister listed below. Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31-16 R/W R/W PHY Data When write, this field specifies the data written to PHY register. When read, this field contains the data returned by PHY. Reserved R/W R/W Register Address of PHY Indicates the offset of PHY register. Access CMD to PHY When ` 1 , HW will issue a read operation to PHY registers, when ' ` 0 , HW will issue a write operation. This field is valid only when bit ' 4 is ` 1 . ' SW Access Request/HW Done When SW wants to access PHY register, it sets this bit to request HW. For such operation, HW will perform the access operation in a proper time, when finished, it clears this bit. SW can' t change the PHY access contents if the current access is not done. Reserved
15-11 10-6 5
4
R/W
3-0
Register 20h Transmit Descriptor Pointer Default Value: 00000000h Access: Read/Write This register points to the current Transmit Descriptor. Bit 31-2 Access R/W Description Transmit Descriptor Pointer The current value of transmitter descriptor pointer. When the transmit state machine is idle, software must set TXDP to the address of a completed transmit descriptor. While the transmit state machine is active, TXDP will follow the state machine as it advances through a linked list of active descriptors. If the link field of the current transmit descriptor is NULL (signifying the end of the list), TXDP will not advance, but will remain on the current descriptor. Any subsequent writes to the TXE bit of the CR register will cause the transmit state machine to reread the link field of the current descriptor to check for new descriptors that may have been appended to the end of the list. Transmit descriptors must be aligned on an even 32-bit boundary in host memory (A1-A0 must be 0). Reserved Transmit Configuration 259 Silicon Integrated Systems Corporation
1-0 Register 24h
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Default Value: 00800102h Access: Read/Write This register defines the Transmit Configuration for The SiS Ethernet Controller. It controls such functions as Loopback, Auto Transmit Padding, Fill & Drain Thresholds, and maximum DMA burst size. Bit 31 Access R/W Description Carrier Sense Ignore Setting this bit to 1 causes the transmitter to ignore carrier sense activity, which inhibits reporting of CRS status to the transmitter status register. When this bit is 0 (default), the transmitter will monitor the CRS signal during transmission and reflect valid status in the transmitter status register. This bit must be set to enable full-duplex operation. HeartBeat Ignore Setting this bit to 1 causes the transmitter to ignore the heartbeat (CD) pulse that follows the packet transmission. When this bit is set to 0 (default), the transmitter will monitor the heartbeat pulse. This bit must be set to enable full-duplex operation MAC Loopback Setting this bit to a 1 places The SiS Ethernet Controller into a controller loopback state which routes all transmit traffic to the receiver, and disables the transmit and receive interfaces of the MII. A 0 in this bit allows normal MAC operation. The transmitter and receiver must be disabled before enabling the loopback mode. (Packets received during MLB mode will reflect loopback status in the receive descriptor` s CMDSTS.LBP field.) Automatic Transmit Padding Setting this bit to 1 causes the MAC to automatically pad small (runt) transmit packets to the Ethernet minimum size of 64 bytes. This allows driver software to transfer only actual packet data. Setting this bit to 0 disables the automatic padding function, forcing software to control runt padding. Reserved Writes are ignored, reads return 01.
30
R/W
29
R/W
28
R/W
27-25 24-23
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 22-20 R/W Max DMA Burst Size per TX DMA Burst This field sets the maximum size of transmit DMA data bursts according to the following table: 000 001 010 011 100 101 110 111 19-14 13-8 R/W Reserved TX Fill Threshold Specifies the fill threshold in units of 32 bytes. When the number of available bytes in the transmitter FIFO reaches this level, the transmit bus master state machine will be allowed to request the PCI bus for transmit packet fragment reads. A value of 0 in this field will produce unexpected results and must not be used. Reserved R/W TX Drain Threshold Specifies the drain threshold in units of 32 bytes. When the number of bytes in the FIFO reaches this level (or the FIFO contains at least one complete packet) the MAC transmit state machine will begin the transmission of a packet. NOTE: In order to prevent a deadlock condition from occurring, the transmit drain threshold should never be set higher than the (TXFIFOSize - TXCFG:FLTH). A value of 0 in this field will produce unexpected results and must not be used. 128 x 32-bit words (512 bytes) 1 x 32-bit word (4 bytes) 2 x 32-bit words (8 bytes) 4 x 32-bit words (16 bytes) 8 x 32-bit words (32 bytes) 16 x 32-bit words (64 bytes) 32 x 32-bit words (128 bytes) 64 x 32-bit words (256 bytes)
7-6 5-0
Register 30h This register points to the current Receive Descriptor. Default Value: 00000000h Access: Read/Write This register points to the current Receive Descriptor. Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31-2 R/W Receive Descriptor Pointer The current value of the receiver descriptor pointer. When the receive state machine is idle, software must set RXDP to the address of an available receive descriptor. While the receive state machine is active, RXDP will follow the state machine as it advances through a linked list of available descriptors. If the link field of the current receive descriptor is NULL (signifying the end of the list), RXDP will not advance, but will remain on the current descriptor. Any subsequent writes to the RXE bit of the CR register will cause the receive state machine to reread the link field of the current descriptor to check for new descriptors that may have been appended to the end of the list. Software should not write to this register unless the receive state machine is idle. Receive descriptors must be aligned on 32-bit boundaries (A1-A0 must be zero). Reserved
1-0
Register 34h Receive Configuration Default Value: 00000002h Access: Read/Write This register is used to set the receiver configuration for The SiS Ethernet Controller. Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here. Bit 31 Access R/W Description Accept Errors Packets When set to 1, all packets with CRC, alignment, and/or collision errors will be accepted. When set to 0, all packets with CRC, alignment, and/or collision errors will be rejected if possible. Note that depending on the type of error, some packets may be received with errors, regardless of the setting of AEP. These errors will be indicated in the CMDSTS field of the last descriptor in the packet. Accept Runt Packets When set to 1, all packets under 64 bytes in length without errors are accepted. When this bit is 0, all packets less than 64 bytes in length will be rejected if possible. Reserved
30
R/W
29
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 28 R/W Accept Transmit Packets When set to 1, data received simultaneously to a local transmission (such as during a PMD loopback or full duplex operation) will be accepted as valid received data. Additionally, when set to 1, the receiver will ignore collision activity. When set to 0 (default), all data receive simultaneous to a local transmit will be rejected. This bit must be set to 1 for PMD loopback and full duplex operation. Accept Jabber Packets When set to 1, all packets over 1518 bytes in length (to a maximum of 2046 bytes) will be accepted and placed in the receive data buffers (if buffers that large are specified in the receive descriptor list). When set to 0, packets larger than 1518 bytes (CRC inclusive) will be rejected if possible. A byte count of 2046 indicates that the packet may have been truncated. Reserved R/W Max DMA Burst Size per RX DMA Burst This field sets the maximum size of receive DMA data bursts according to the following table: 000 128 x 32-bit words (512 bytes) 001 1 x 32-bit word (4 bytes) 010 2 x 32-bit words (8 bytes) 011 4 x 32-bit words (16 bytes) 100 8 x 32-bit words (32 bytes) 101 16 x 32-bit words (64 bytes) 110 32 x 32-bit words (128 bytes) 111 64 x 32-bit words (256 bytes) 19-6 Reserved
27
R/W
26-23 22-20
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5-1 R/W RX Drain Threshold Specifies the drain threshold in units of 8 bytes. When the number of bytes in the receiver FIFO reaches this value (times 8), or the FIFO contains a complete packet, the receive bus master state machine will begin the transfer of data from the FIFO to host memory. Care must be taken when setting DRTH to a value lower than the number of bytes needed to determine if packet should be accepted or rejected. In this case, the packet might be rejected after the bus master operation to begin transferring the packet into memory has begun. When this occurs, neither the OK bit nor any error status bit in the descriptor' s CMDSTS will be set. A value of 0 is illegal, and the results are undefined. This value is also used to compare with the accumulated packet length for early receive indication. When the accumulated packet length meets or exceeds the DRTH value, the RXEARLY interrupt condition is generated. Reserved
0
Register 38h Flow Control Default Value: 00000000h Access: Read/Write The FLOWCTL register is used to control and configure The SiS Ethernet Controller Flow Control logic. The Flow Control Logic is used to detect PAUSE frame packets and control data frame transmission. Bit 31-2 1 R/W Access Reserved PAUSE Flag When "1" indicates data frame transmission is paused. When "0" transmission is normal. This bit is reset by H/W reset, 900 soft reset, transmit reset, pause timer expires or S/W write 0 to this bit. Flow Control Enable Set to 1, enable the PAUSE frame detection. Set to 0, disable the PAUSE frame detection. This bit is reset only by H/W reset. Description
0
R/W
Register 48h Receive Filter Control Default Value: 00000000h Access: Read/Write The RFCR register is used to control and configure The SiS Ethernet Controller Receive Filter Control logic. The Receive Filter Control Logic is used to configure destination address filtering of incoming packets. Preliminary V.10 Oct.07,1999 264 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bit 31 Access R/W Description RX Filter Enable When this bit is set to 1, the RX Filter is enabled to qualify incoming packets. When set to 0, receive packet filtering is disabled (i.e. all receive packets are rejected). Accept All Broadcast When set to 1, this bit causes all broadcast address packets to be accepted. When set to 0, no broadcast address packets will be accepted. Accept All Multicast When set to 1, this bit causes all multicast address packets to be accepted. When set to 0, multicast destination addresses must have the appropriate bit set in the multicast hash table mask in order for the packet to be accepted. Accept All Physical When set to 1, this bit causes all physical address packets to be accepted. When set to 0, the destination address must match the node address register in order for the packet to be accepted. HomePHY Or 802.3u PHY Select When set to 1, HomePHY is selected and set to 0 to select 802.3u PHY. Reserved
30
R/W
29
R/W
28
R/W
27
R/W
26-20
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 19-16 R/W Receive Filter Address Selects which internal receive filter register is accessible via RFDR: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 others 15-0 Reserved node address octets 1-0 node address octets 3-2 node address octets 5-4 RESERVED multicast hash table bits 15-0 multicast hash table bits 31-16 multicast hash table bits 47-32 multicast hash table bits 63-48 multicast hash table bits 79-64 multicast hash table bits 95-80 multicast hash table bits 111-96 multicast hash table bits 127-112 RESERVED
Register 4Ch Receive Filter Data Default Value: 00000000h Access: Read/Write The RFDR register is used for reading from and writing to the internal receive filter registers (unique address register, and the hash table register). Bit 31-16 15-0 R/W Access Reserved Receiver Filter Data Receiver Filter Data The Receive Filter Logic uses the following algorithm when qualifying incoming packets for reception: Description
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START
Is DA a Muticast? YES
NO
Is AAP set? YES Accept Packet
NO
Is DA=NA ? YES Accept Packet
NO
Reject Packet
Is DA a NO Broadcast? YES
Is AAM set? YES Accept Packet
NO
Hash Table bit set? YES Accept Packet
NO
Reject Packet
Is AAB set?
NO
Reject Packet
YES Accept Packet
Figure 13.4-1 Receive Filter Algorithm The Node Address register is a 48-bit register internal to the Receive Filter logic. When RFCR:AAP is clear, then the receive filter logic will only accept unicast packets which match the contents of the node address register. Octet 0 of the node address register corresponds to the first octet of the packet as it appears on the wire. Octet 5 of the node address register corresponds to the last octet of the destination address as it appears on the wire. For example, to configure a node address of 00-E0-06-07-28-55, Software will need to execute the following series of register operations:
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octet 0 00000000 00 1 11100000 E0 2 00000110 06 3 4 5 01010101 55
00000111 00101000 07 28
(as it appears on the wire)
out32( RFCR, 0x00000000 ); /* disable receive filter, NA(0) */ out32( RFDR, 0x0000E000 ); /* load octets 0 and 1 */ out32( RFCR, 0x00010000 ); /* select NA[1] */ out32( RFDR, 0x00000706 ); /* load octets 2 and 3 */ out32( RFCR, 0x00020000 ); /* select NA[2] */ out32( RFDR, 0x00005528 ); /* load octets 4 and 5 */ out32( RFCR, 0xC0000000 ); /* enable receive filter, accept broadcasts */ The Multicast Hash Table register can be configured to perform imperfect filtering of multicast packets. If the receive packet` s destination address is a multicast address (but not the broadcast address) and the RFCR:AAM is not set, then the receive filter logic will use the 7 most significant bits of the destination address' s CRC as an index into the Multicast Hash Table register. If the corresponding bit is set, then the packet is accepted, otherwise the packet is rejected. Refer to Appendix B - Hash Table Index Computation. Register B0h Power Management Control Default Value: 00000000h Access: Read/Write This register provides SW an interface to control which Power Management Event to assert PME# / INTA#. The contents of this register should be well-programmed before set the Ethernet Controller into power saving state, and will not be affected by PCI HW reset. It can be reset by software reset (OP register offset 00h bit8) except ISOSEL. Bit 31 Access R/W Description Gate Dual Target Clock Enable When ` 1 , the clock of dual powered blocks will be gated when in ' (D3cold and (not PME_EN)). When ` 0 , the clock of dual powered ' blocks will never be gated. Wake-up While Receive OK Packet When ` 1 , any packet that passed the RXFilter with no error will ' cause a wake-up event. This may include any broadcast, multicast, or direct addressed packet depending on how RXFilter is programmed. Reserved
30
R/W
29-27
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 26 R/W 3rd Wake-up Frame Access When ` 1 , access to WAKECRC is indirectly mapped to the 3rd ' wake-up frame CRC register. FRM3ACS, FRM2ACS, and FRM1ACS are supposed not to be set at the same time for read access. 2nd Wake-up Frame Access When ` 1 , access to WAKECRC is indirectly mapped to the 2nd ' wake-up frame CRC register. FRM3ACS, FRM2ACS, and FRM1ACS are supposed not to be set at the same time for read access. 1st Wake-up Frame Access When ` 1 , access to WAKECRC is indirectly mapped to the 1st ' wake-up frame CRC register. FRM3ACS, FRM2ACS, and FRM1ACS are supposed not to be set at the same time for read access. Reserved R/W 3rd Wake-up Frame Match Enable When this bit is ` 1 , and PME_EN is ` 1 , the 3rd wake-up ' ' mechanism of receipt of a network wake-up frame is enabled. 2nd Wake-up Frame Match Enable When this bit is ` 1 , and PME_EN is ` 1 , the 2nd wake-up ' ' mechanism of receipt of a network wake-up frame is enabled. 1st Wake-up Frame Match Enable When this bit is ` 1 , and PME_EN is ` 1 , the 1st wake-up ' ' mechanism of receipt of a network wake-up frame is enabled. Reserved R/W Magic PacketTM Match Algorithm When ` 1 , a strict magic packet match algorithm is used when ' detect magic packet. When ` 0 , a loose magic packet match algorithm is used when ' detects magic packet. 10 R/W Magic PacketTM Match Enable When this bit is ` 1 , and PME_EN is ` 1 , the wake-up mechanism of ' ' receipt of a Magic Packet is enabled. Reserved
25
R/W
24
R/W
23 22
21
R/W
20
R/W
19-12 11
9-2
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1 R/W Link On Monitor Enable When this bit is ` 1 , and PME_EN is ` 1 , the wake-up mechanism of ' ' detection the link on state is enabled. 0 R/W Link Loss Monitor Enable When this bit is ` 1 , and PME_EN is ` 1 , the wake-up mechanism of ' ' detection the link loss state is enabled.
Register B4h Power Management Wake-up Event Default Value: 00000000h Access: Read/Write This register records which wake-up event wake up the system. This register is not affected by PCI HW reset. It can be reset only by software reset (OP register offset 00h bit8). SW writes 1 will clear the individual bits. SW writes 0 will leave the individual bits unchanged. Bit 31 30 R/W Access Reserved Receive OK Packet H/W sets this bit whenever bit30 of PM Control Register is ` 1 and ' an incoming packet passes the RXFilter with no error. SW writes ` 1 to this bit will clear this bit. SW writes ` 0 to this bit ' ' leaves this bit unchanged. 29-23 22 R/W Reserved Match 3rd Wake-up Sample Frame H/W sets this bit whenever bit22 of PM Control Register is ` 1 and ' receipt of the pre-defined 3rd wake-up frame with no error. SW writes ` 1 to this bit will clear this bit. SW writes ` 0 to this bit ' ' leaves this bit unchanged. 21 R/W Match 2nd Wake-up Sample Frame H/W sets this bit whenever bit21 of PM Control Register is ` 1 and ' receipt of the pre-defined 2nd wake-up frame with no error. SW writes ` 1 to this bit will clear this bit. SW writes ` 0 to this bit ' ' leaves this bit unchanged. 20 R/W Match 1st Wake-up Sample Frame H/W sets this bit whenever bit20 of PM Control Register is ` 1 and ' receipt of the pre-defined 1st wake-up frame with no error. SW writes ` 1 to this bit will clear this bit. SW writes ` 0 to this bit ' ' leaves this bit unchanged. Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 19-11 10 R/W Reserved Magic PacketTM Match H/W sets this bit whenever bit10 of PM Control Register is ` 1 and ' receipt of a magic packet with no error. SW writes ` 1 to this bit will clear this bit. SW writes ` 0 to this bit ' ' leaves this bit unchanged. 9-2 1 R/W Reserved Link On Event H/W sets this bit whenever bit1 of PM Control Register is ` 1' and link status changes from loss to on. SW writes ` 1 to this bit will clear this bit. SW writes ` 0 to this bit ' ' leaves this bit unchanged. 0 R/W Link Loss Event H/W sets this bit whenever bit0 of PM Control Register is ` 1' and link status changes from on to loss. SW writes ` 1 to this bit will clear this bit. SW writes ` 0 to this bit ' ' leaves this bit unchanged. Register BCh Wake-up Sample Frame CRC Default Value: 00000000h Access: Read/Write This register provides an access window to the CRC values of the mask bytes in wake-up sample frames. When FRM3ACS, FRM2ACS, or FRM1ACS is ` 1 , the CRC value of the mask ' bytes in the corresponding wake-up sample frame can be accessed through this register. FRM3ACS, FRM2ACS, and FRM1ACS are supposed not to be set at the same time for read access. If the CRC value of those incoming bytes, whose byte mask is set to 1 in the sample frame, equals to the CRC value in the sample frame, then the incoming frame is considered a wake-up frame. This register is not affected by PCI HW reset. It can be reset only by software reset (OP register offset 00h bit8). Bit 31-0 Access R/W Description Wake-up Frame CRC Value This field specifies the CRC value of the mask bytes in the corresponding wake-up sample frame specified by FRM3ACS, FRM2ACS, and FRM1ACS. H/W uses this 32-bit CRC value to match the 32-bit CRC value of incoming frame mask bytes. If matched, the incoming frame is a wake-up frame and PME# will be asserted if enabled.
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 13.4.1 Wake-up Sample Frame Byte Mask Register These registers provide the mask bytes in wake-up sample frames. These registers are not affected by PCI HW reset. They can be reset by software reset (OP register offset 00h bit8). Register C0h C4h C8h CCh D0h D4h D8h DCh E0h E4h E8h ECh Size 32 32 32 32 32 32 32 32 32 32 32 32 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description The 1st 32 byte mask in the 1st Wake-up sample frame. The 2nd 32 byte mask in the 1st Wake-up sample frame. The 3rd 32 byte mask in the 1st Wake-up sample frame. The 4th 32 byte mask in the 1st Wake-up sample frame. The 1st 32 byte mask in the 2nd Wake-up sample frame. The 2nd 32 byte mask in the 2nd Wake-up sample frame. The 3rd 32 byte mask in the 2nd Wake-up sample frame. The 4th 32 byte mask in the 2nd Wake-up sample frame. The 1st 32 byte mask in the 3rd Wake-up sample frame. The 2nd 32 byte mask in the 3rd Wake-up sample frame. The 3rd 32 byte mask in the 3rd Wake-up sample frame. The 4th 32 byte mask in the 3rd Wake-up sample frame.
13.5
MII PHY Registers
SiS540 has eleven internal MII PHY 16 bit registers. Ten registers are available for setting configuration inputs and reading status outputs and one register is reserved for factory use. The ten accessible registers consist of six registers that are defined by IEEE 802.3 specification (MI Register 0-5) and four registers that are unique to SiS540 (MI Register 1619). The accesses of the ten MI PHY Registers are through MAC Operational Register ENPHY (offset 1Ch). Users can define the command (RWCMD, ENPHY bit 5), the Register Offset (REGADDR, ENPHY bit 10-6), and the Data contents (PHYDATA, ENPHY bit 31-16). And then the driver issue the access command bit by writing ` 1' to register ENPHY bit 4, ACCESS, and wait for SiS540 complete the operation which should return ` 0' when completed. Table 13.5-1 PHY Configuration Register Map Register 00h 01h 02h 03h 04h Tag CONTROL STATUS PHYID1 PHYID2 AUTOADV Description MI Register 0 Control Register MI Register 1 Status Register MI Register 2 PHY ID#1 MI Register 3 PHY ID#2 MI Register 4 Auto Negotiation 272 Access RO R/W RO R/W R/W Section 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Advertisement 05h 10h 11h 12h 13h 14h AUTOREC CONFIG1 CONFIG2 STSOUT MASK RESERVED MI Register 5 Auto Negotiation Remote End Capability MI Register 16 Configuration 1 MI Register 17 Configuration 2 MI Register 18 Status Output MI Register 19 Mask MI Register 20 Reserved R/W R/W R/W R/LT R/W R/W 4.4.6 4.4.7 4.4.8 4.4.9 4.4.10 4.4.11
Register 00h CONTROL Default Value: 3000h Access: Read/Write Bit 15 Access R/WSC PHY Reset 1: Reset, Bit Self Cleaning After Reset Completed 0: Normal 14 R/W Loopback 1: Loopback Mode Enabled 0: Normal 13 R/W Speed 1: 100 Mbps Selected (100Base TX) 0: 10 Mbps selected (10Base-T) 12 R/W Auto-Negotiation 1: Auto-Negotiation Enabled 0: Normal 11 R/W Powerdown 1: Powerdown 0: Normal 10 R/W MII interface 1: MII Interface Disabled 0: Normal Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 9 R/WSC Auto-Negotiation Reset 1: Reset Auto-Negotiation Process, Bit Self Clearing After Reset Completed 0: Normal 8 R/W Duplex Mode 1: Full Duplex 0: Half Duplex 7 R/W Collision Test 1: Collision Test Enabled 0: Normal 6-0 R/W Reserved
Register 01h STATUS Default Value: 7809h Access: Read Only Bit 15 14 13 12 11 10-7 6 5 4 Access RO RO RO RO RO RO R R R/LH Description 0: Not Capable of 100Base-T4 Operation 1: Capable of 100Base-TX Full Duplex 1: Capable of 100Base-TX Half Duplex 1: Capable of 10Base-T Full Duplex 1: Capable of 10Base-T Half Duplex Reserved 0: Not Capable of Accepting MI Frames with MI Preamble Suppressed 1: Auto-Negotiation Acknowledge Process Complete 0: Normal 1: Remote Fault Detected. This bit is set when Either Interrupt Detect or Auto-Negotiation Remote Fault is set. 0: No Remote Fault 1: Capable of Auto-Negotiation Operation 1: Link Detected 0: Link not detected
3 2
R R/LL
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Register 02h PHY ID #1 Default Value: 001Dh Access: Read Bit 15-0 Access R Company ID, Bits 3-18 OUI = 00-E0-06 Register 03h PHY ID #2 Default Value: 8000h Access: Read Bit 15-10 Access R Description Company ID, Bits 19-24 OUI = 00-E0-06 9-4 R Manufacturer's Part Number 00 H 3-0 R Manufacturer's Revision Number 00 H Register 04h Auto-Negotiation Advertisement Default Value: 05E1h Access: Read/Write Bit 15 14 13 12-11 Access R/W R R/W R/W Description 1: Next Page Exists 0: No Next Page 1: Received Auto-Negotiation Word Recognized 0: Not Recognized 1: Auto-Negotiation Remote Fault Detected 0: No Remote Fault RESERVED Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 10 9 8 7 6 5 4-1 0 R/W R/W R/W R/W R/W R/W R/W R/W 1: Capable of Pause Operation for Full Duplex Link 0: Not Capable 1: Capable of 100Base-T4 0: Not Capable 1: Capable of 100Base-TX Full Duplex 0: Not Capable 1: Capable of 100Base-TX Half Duplex 0: Not Capable 1: Capable of 10Base-T Full Duplex 0: Not Capable 1: Capable of 10Base-T Half Duplex 0: Not Capable RESERVED 1: Capable of 802.3 CSMA Operation 0: Not Capable
NOTE 1: NEXT PAGE CURRENTLY NOT SUPPORTED. Register 05h Auto-Negotiation Remote End Capability Default Value: 0000h Access: Read Bit 15 14 13 12-11 10 9 Access R R R R R R Description 1: Next Page Exists 0: No Next Page 1: Received Auto-Negotiation Word Recognized 0: Not Recognized 1: Auto-Negotiation Remote Fault Detected 0: No Remote Fault Reserved 1: Capable of Pause Operation for Full Duplex Link 0: Not Capable 1: Capable of 100Base-T4 0: Not Capable
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 8 7 6 5 4-1 0 R R R R R R 1: Capable of 100Base-TX Full Duplex 0: Not Capable 1: Capable of 100Base-TX Half Duplex 0: Not Capable 1: Capable of 10Base-T Full Duplex 0: Not Capable 1: Capable of 10Base-T Half Duplex 0: Not Capable RESERVED 1: Capable of 802.3 CSMA Operation 0: Not Capable
Register 10h Configuration 1 Default Value: 0022h Access: Read/Write Bit 15 Access R/W Link Disable 1: Received Link Detect Function Disabled (Force Link Pass) 0: Normal 14 R/W Transmit Disable 1: TP Transmitter Disabled 0: Normal 13 R/W Transmit Powerdown 1: TP Transmitter Powered Down 0: Normal 12 R/W TX_EN to CRS Loopback 1: TX_EN to CRS Loopback Disabled 0: Enabled 11-10 R/W RESERVED Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 9 R/W Unscrambled Idle Reception Disable 1: Disable Auto-Negotiation with devices that transmit unscrambled, idle on power up and various instances 0: Enables Auto-Negotiation with devices that transmit unscrambled, idle on power up and various instances 8 R/W Receive Equalizer Select 1: Received Equalizer Disabled, Set to 0 Length 0: Receive Equalizer On (For 100Base-TX Mode Only) 7 R/W Cable Type Select 1: STP (150 Ohm) 0: UTP (100 Ohm) 6 R/W Receive Input Level Adjust 1: Receive Squelch Levels Reduced By 4.5 dB 0: Normal 5-2 1-0 R/W R/W Reserved Transmitter Rise/Fall Time Adjust 11 10 01 00 Register 11h Configuration 2 Default Value: FF00h Access: Read/Write Bit 15-6 5 Access R R/W Reserved Auto Polarity Disable 1: Auto Polarity Correction Function Disabled 0: Normal 4 R/W Jabber Disable Select 1: Jabber Disabled 0: Enabled 3-0 R/W Reserved Description -0.25 ns +0.0 ns +0.25 ns +0.5 ns
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 12h Status Output REGISTER Default Value: 0080h Access: Read Only Bit 15 Access RO Interrupt Detect 1: Interrupt Bit(s) Have Changed Since Last Read Operation. 0: No Change 14 R/LT Link Fail Detect 1: Link Not Detected 0: Normal 13 R/LT Descrambler Loss of Synchronization Detect 1: Descrambler Has Lost Synchronization 0: Normal 12 R/LT Codeword Error 1: Invalid 4B/5B Code Detected On Receive Data 0: Normal 11 R/LT Start Of Stream Error 1: No Start Of Stream Delimiter Detected on Received Data 0: Normal 10 R/LT End Of Stream Error 1: No End Of Stream Delimiter Detected On Receive Data 0: Normal 9 R/LT Reverse Polarity Detect 1: Reserve Polarity Detected 0: Normal 8 R/LT Jabber Detect 1: Jabber Detected 0: Normal 7 R/LT 100/10 Speed Detect 1: Device in 100 Mbps Mode (100Base-TX) 0: Device in 10 Mbps Mode (10Base-T) Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 6 R/LT Duplex Detect 1: Device In Full Duplex 0: Device In Half Duplex 5-4 RO Auto-Negotiation Status 11 10 01 00 3-0 RO Auto-Negotiation Detected & Started Auto-Negotiation Detected & Stuck Auto-Negotiation Detected & Done Auto-Negotiation Not Detected
Reserved
Register 13h Mask Default Value: FFC0h Access: Read/Write Bit 15 14 Access R/W R/W Description 1: Mask Interrupt For INT in Register 18 0: No Mask 1: Mask Interrupt For LNK_FAIL in Register 18 0: No Mask 13 12 11 10 9 8 7 R/W R/W R/W R/W R/W R/W R/W 1: Mask Interrupt For LOSS_SYNC in Register 18 0: No Mask 1: Mask Interrupt For CWRD in Register 18 0: No Mask 1: Mask Interrupt For SSD in Register 18 0: No Mask 1: Mask Interrupt For ESD in Register 18 0: No Mask 1: Mask Interrupt For RPOL in Register 18 0: No Mask 1: Mask Interrupt For JAB in Register 18 0: No Mask 1: Mask Interrupt For SPD_DET in Register 18 0: No Mask
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 6 5-3 2-0 R/W R/W R/W 1: Mask Interrupt For DPLX_DET in Register 18 0: No Mask Reserved Link Fail Timer Select 111 110 101 100 011 010 001 000 Register 14h RESERVED Default Value: 0000h Access: Read/Write Bit 15-0 Access R/W Description Reserved for Factory Use. Must to 0 for Normal Operation Reserved Bit 18.14 Set to 1 if Link Fail for >32 Sec Bit 18.14 Set to 1 if Link Fail for >16 Sec Bit 18.14 Set to 1 if Link Fail for >8 Sec Bit 18.14 Set to 1 if Link Fail for >4 Sec Bit 18.14 Set to 1 if Link Fail for >2 Sec Bit 18.14 Set to 1 if Link Fail for >1 Sec Bit 18.14 Set to 1 if Link Fail for >0 Sec
13.6
Home SPI Registers
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W STATUS Register IMASK Register ISTAT Register TX_PCOM Register RX_PCOM Register NOISE Register PEAK Register NSE_FLOOR Register NSE_CEILING Register NSE_ATTACK Register 281 Silicon Integrated Systems Corporation Register Name CONTROL Register
(These registers can be accessed from MAC serial EEPROM interface) Address 01h-00h 03h-02h 05h-04h 07h-06h 0Bh-08h 0Fh-0Ch 10h 11h 12h 13h 14h
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 15h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh R/W R/W R/W R/W R/W R/W R/W R/W NSE_EVENTS Register AID_ADDRESS Register AID_INTERVAL Register AID_ISBI Register ISBI_SLOW Register ISBI_FAST Register TX_PULSE_WIDTH Register TX_PULSE_CYCLES Register
Register 00h CONTROL Default Value: 05 Access: Read / Write Bit 7 Access R/W Description Disable AID Address Negotiation 0 : normal 1 : disable Clear the NSE_EVENTS Register 0 : normal 1 : clear Disable SLICE Adaptation 0 : normal 1 : disable Power down 0 : normal 1 : power down Reserved High Speed 0 : low speed 1 : high speed High Power 0 : low power 1 : high power Reserved
6
R/W
5
R/W
4
R/W
3 2
R/W R/W
1
R/W
0 Register 01h
R/W
CONTROL 282 Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Default Value: 00 Access: Read / Write Bit 7 Access R/W Set Remote Command 0 : disable 1 : enable 6-4 3 R/W R/W Reserved Command Low Power 0 : normal 1 : set low power command 2 R/W Command High Power 0 : normal 1 : set high power command 1 R/W Command Low Speed 0 : normal 1 : set low speed command 0 R/W Command High Speed 0 : normal 1 : set high speed command Register 02h STATUS Default Value: 00 Access: Read / Write Bit 7 6 Access R/W R/W Reserved RX_POWER 0 : receive low power 1 : receive high power 5 R/W RX_SPEED 0 : receive low speed 1 : receive high speed 4 R/W RX_VERSION 0 : version 0 1 : not version 0 Preliminary V.10 Oct.07,1999 283 Silicon Integrated Systems Corporation Description Description
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3-0 R/W Reserved
Register 03h STATUS Default Value: 00 Access: Read / Write Bit 7-0 Access R/W Reserved Description
Register 04h IMASK Default Value: 00 Access: Read / Write Bit 7-4 3 Access R/W R/W Reserved Receive Packet 0 : mask 1 : no mask 2 R/W Transmit Packet 0 : mask 1 : no mask 1 R/W Receive Remote Command 0 : mask 1 : no mask 0 R/W Sent Remote Command 0 : mask 1 : no mask Register 05h IMASK Default Value: 00 Access: Read / Write Bit 7-2 1 Access R/W R/W Reserved RxPCOM 0 : mask 1 : no mask Description Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 R/W TxPCOM 0 : mask 1 : no mask
Register 06h ISTAT Default Value: 00 Access: Read / Write Bit 4-7 3 Access R/W R/W Reserved Packet Rcv' d 0 : no receive packet 1 : receive packet done Packet Xmt' d 0 : no transmit packet 1 : transmit packet done Receive Remote Command Valid 0 : no complete 1 : complete Sent Remote Command Done 0 : no complete 1 : complete Description
2
R/W
1
R/W
0
R/W
Register 05h ISTAT Default Value: 00 Access: Read / Write Bit 7-2 1 Access R/W R/W Reserved RxPCOM Valid 0 : all 0 data 1 : non-null data TxPCOM Ready 0 : all 0 data 1: non-null data Description
0
R/W
Register 0Bh~08h TX_PCOM Default Value: 00000000 Access: Read / Write Preliminary V.10 Oct.07,1999 285 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bit 31:0 Access R/W Description The 32-bit transmitted data field to be used for out-of-band communication between HOMEPHY management entities.
Register 0Fh~0Ch RX_PCOM Default Value: 00000000 Access: Read / Write Bit 31:0 Access R/W Description The 32-bit received data field to be used for out-of-band communication between HOMEPHY management entities.
Register 10h NOISE Default Value: 04 Access: Read / Write Bit 7:0 Access R/W Description This is the digital value of the SLICE_LVL_NOISE output. When the bit 5 of the 00h register is false, this register is updated with current NOISE LEVEL every 50ns. When the bit 5 of the 00h register is true, this register is used to genertae both the SLICE_LVL_NOISE and SLICE_LVL_DATA. Register 11h PEAK Default Value: FF Access: Read / Write Bit 7:0 Access R/W Description This is a measurement of the peak level of the AID received (non-collision).
Register 12h NSE_FLOOR Default Value: 04 Access: Read / Write Bit 7:0 Access R/W Description The minimum value of the NOISE measurement.
Register 13h NSE_CEILING Default Value: FF Access: Read / Write
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bit 7:0 Access R/W Description The value that is reload into PEAK register if NOISE level exceeds PEAK level.
Register 14h NSE_ATTACK Default Value: F4 Access: Read / Write Bit 7:4 3:0 Access R/W R/W Description This value define the number of noise events need to raise the SLICE LEVEL immediately. This value define the number of noise events need to raise the SLICE LEVEL at the end of an 870ms period.
Register 15h NSE_EVENTS Default Value: 00 Access: Read / Write Bit 7:0 Access R/W Description The value record the number of noise event detected.
Register 19h AID_ADDRESS Default Value: 00 Access: Read / Write Bit 7:0 Access R/W Description The AID address is used for collision detection. Unless bit 7 of the 00h register is set, the HOMEPHY is assured to select unique AID address. Register 1Ah AID_INTERVAL Default Value: 14 Access: Read / Write Bit 7:0 Access R/W Description The value defines the number of TCLK separating AID symbols.
Register 1Bh AID_ISBI Default Value: 40 Access: Read / Write Bit Access 287 Description Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:0 R/W The value defines the number of TCLK between AID pulse for symbol 0.
Register 1Ch ISBI_SLOW Default Value: 2C Access: Read / Write Bit 7:0 Access R/W Description The value defines the number of TCLK between DATA pulse for symbol 0 in low speed.
Register 1Dh ISBI_FAST Default Value: 1C Access: Read / Write Bit 7:0 Access R/W Description The value defines the number of TCLK between DATA pulse for symbol 0 in high speed.
Register 1Eh TX_PULSE_WIDTH Default Value: 04 Access: Read / Write Bit 7:0 Access R/W Description The value determines the number of OSC cycles a transmit pulse lasts.
Register 1Fh TX_PULSE_CYCLES Default Value: 04 Access: Read / Write Bit 7:4 3:0 Access R/W R/W Description The value determines the number of pulse on TXP. The value determines the number of pulse on TXN.
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14
14.1
Register Summary / Description - Audio Accelerator Summary
Audio Configuration Space ( Function 4)
Access R/W R/W R/W R/W RO RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W RO RO RO R/W R/W R/W R/W R/W R/W R/W 289 Mnemonic Register Vendor ID Device ID Command Status Revision ID Class Code Cache Line Size Latency Timer Header Type BIST Audio IO Base Address Audio Memory Base Address RSVD Subsystem Vendor ID Subsystem ID RSVD Power Management Capability List Pointer RSVD RSVD Interrupt Line Interrupt Pin MIN_GNT MAX_LAT DDMA Slave Configuration Legacy I/O base decoding Legacy DMA decoding Silicon Integrated Systems Corporation
Configuration. Offset 00-01h 02-03h 04-05 06-07h 08h 09-0Bh 0Ch 0Dh 0Eh 0Fh 10-13h 14-17h 18-2Bh 2C-2Dh 2E-2Fh 30-33h 34h 35-37h 38-3Bh 3Ch 3Dh 3Eh 3Fh 40-43h 44h 45h Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 46h 47h 48-49h 4A-4Bh 4C-DBh DC-DFh E0-E3h R/W R/W R/W RO RO R/W R/W Power Management Configuration Inactivity Timer Expiration Control INT Acknowledge Snoop RSVD RSVD Power Management Capability Register Power management control/status Register
14.1.1 Audio Configuration Registers: Register 00h Device ID & Vendor ID Default Value: 70181039h Access: read/write, can be written only when CFG46h[6]=1 Bit 31:16 15:0 Access R/W R/W Description Device ID: default 7018h Vendor ID: default 1039h
Register 04h Status & Command Default: 02900000h Description: Read/Write Bit 1-0 2 20 23,25 28 29 Access R/W R/W R/W R/W R/W R/W Bus Master. Write 0 to this bit can not disable bus mastering. PM PCI Power Management support, hardwired to 1 hardwired to 1 TA Received target abort. Write 1 to clear. MA Received master abort. Write 1 to clear. Description
The rest bits are hardwired to 0 Register 08h-0Bh Status & Command Default Value: 04010001h Access: read only Bit 7:0 Access RO 01 Revision ID 290 Silicon Integrated Systems Corporation Description
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 15:8 23:16 31:24 RO RO RO 00 01 Sub-class: Audio device 04 Base class: Multimedia
Register 0Ch BIST, Header Type, Latency Timer & Cache Line Size Legacy Address: Default Value: 00000000h Access: Read/Write Bit 15:12 Access R/W Description
The rest bits are hardwired to 0 Register 10h Audio IO Base Register: Default Value: 00000001h Access: Read/Write Bit 31:8 7:1 0 Access R/W R/W R/W Audio IO base Hardwired to 0 Hardwired to 1 Description
Register 14h Audio MEM Base Register: Default Value: 00000000h Access: Read/Write Bit 31:12 11:0 Access R/W R/W Audio MEM base Hardwired to 0 Description
Register 2Ch Subsystem ID & Subsystem Vendor ID: Default Value: 70181039h Access: read/write, can be written only when CFG46h[6]=1 Bit 31:16 15:0 Access R/W R/W Description Subsystem ID: default 7018h Subsystem vendor ID: default 1039h
Register 34h PCIPM Capability List Pointer Register: Preliminary V.10 Oct.07,1999 291 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Default Value: 000000DCh Access: Read Only Bit 7:0 Access RO Description PCIPM Capability List Pointer Register
Register 3Ch Max_Lat, Min_Gnt, Interrupt Pin & Interrupt Line: Default Value: 18020100h Access: Read /Write Bit 7:0 15:8 23:16 31:24 Access R/W R/W R/W R/W INT line INT pin Min_Gnt Max_Gnt hardwired to 01 hardwired to 02 hardwired to 18 Description
Register 40h DDMA Slave Configuration Register: Default Value: 00000000h Access: Read /Write Bit 31:4 3 Access R/W R/W DDMABase Non Legacy Extended Addressing Control (Fully 32 bit Addressing) 0: disabled 1: enabled 2:1 0 R/W R/W Legacy DMA Transfer Size Control, Read Only as 00 00:8 bit transfer, legacy DDMA Slave Channel Access Enable Control 0: disabled 1: enabled When disabled, the DDMABase is not useful and the PCM sample playback control registers can not be accessed through DDMA Slave channel method. When enabled, SiSAudio can behave like a DDMA Slave channel device. DDMA Master will transfer the legacy DMA controller channel specific information to the related DDMA Slave channel control register when software trying to program the legacy DMA Preliminary V.10 Oct.07,1999 292 Silicon Integrated Systems Corporation Description
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset controller register. Register 44h Legacy I/O Decoding Default Value: E2000000h Access: Read /Write Bit 7 Access R/W 0: MPU401Base disable 1: MPU401Base enable 6 R/W 0: MPU401Base = 0330h-0333h 1: MPU401Base = 0300h-0303h 5 R/W 0: GAMEBase disable 1: GAMEBase enable 4 R/W 0: GAMEBase = 0200h-0207h 1: GAMEBase = 0208h-020Fh 3 R/W 0: ADLIBBase disable 1: ADLIBBase enable 2 R/W 0: ADLIBBase = 0388h-038Bh 1: ADLIBBase = 038Ch-038Fh 1 R/W 0: SBBase disable 1: SBBase enable 0 R/W 0: SBBase = 0220h-022Fh 1: SBBase = 0240h-024Fh Register 45h Legacy DMA Decoding Default Value: E2000000h Access: Read /Write Bit 5:7 Access R/W Reserved Description Description
4
R/W
DMAREG_RD_EN_ 0: Response to DMAREG(00h-03h, 83h/87h) Read when CFG45[1] is 1;
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1: Never response to DMAREG(00h-03h, 83h/87h) Read. 3 R/W 0: DMA status retry OK 1: DMA status retry error If this bit is set, bus interface will not respond to IO8 operation anymore unless the status retry error bit is cleared by writing 1 to this bit. 2 R/W 0: DMA status handle mode A (slave only) 1: DMA status handle mode B (bus master) 1 R/W 0: DMA trapping disable 1: DMA trapping enable 0 R/W 0: DMA channel 1 trapping 1: DMA channel 0 trapping When DMA trapping is enable, the chip will decode the following I/O port DMA channel 1 trapping read 2,3 write snoop 2,3 write snoop 8-Fh write snoop 83h DMA channel 0 trapping read 0,1 write snoop 0,1 write snoop 8-Fh write snoop 87h When DMA trapping is enabled, the chip will handle DMA status read (I/O read port 8) depending on the DMA status mode bit. DMA status handle mode A: SiSAudio will decode I/O read port 8 if StatusRDY is active, otherwise, it will ignore the cycle. DMA status handle mode B: When StatusRDY is not active, the chip will retry DMA status read if it is not the current active bus master. Whenever the chip retries the DMA status read from other bus master, it will also generate a bus request for the DMA status read. When the DMA status read cycle generated by the chip is terminated normally, the chip will write the status data by asserting the StatusWR signal. If the chip retries DMA status read from other bus master 3 times without getting the bus Preliminary V.10 Oct.07,1999 294 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset ownership or proper data, it will set the status error bit high which will terminate the pending DMA status read request internally and ignore the all DMA status read cycle by the other bus master. When audio engine receives the StatusWR signal, it will assert the StatusRDY signal to the chip and allow it to decode I/O read port 8 normally. The audio engine will de-assert the StatusRDY after each DMA status read. NOTE: All I/O decoding is 16-bit, write snooping happen only once even with multiple write retry cycle. Write snooping means the chip will decode the cycle to audio engine without generate the DEVSEL# signal or TRDY# to PCI bus. Register 46h Power Management Configuration (PM_CFG) Default Value: 00h Access: Read /Write Bit 7 Access R/W Description (TIMER_PME_EN) Inactivity Timer assert PME# enable 0: Disable 1: Enable If enabled, PME# will be asserted when Inactivity Timer expired. 6 R/W (ID_WR_EN) Chip IDs write enable 0:Vendor ID, Device ID, Subsystem Vendor ID & Subsystem ID are read only 1:Vendor ID, Device ID, Subsystem Vendor ID & Subsystem ID are writable. Bit 7 (TIMER_PME_EN) Inactivity Timer assert PME# enable 5 R/W (WAKE_EN2) Secondary CODEC Wake-up Enable Powered with Vaux. Cleared when H/W reset or S/W reset. 0: disable 1: enable When CODEC_PD = 1, BCLK keeps low, a rising edge of ACDI2 will set WAVE_EV to high 4 R/W (WAKE_EN1) Primary CODEC Wake-up Enable Powered with Vaux. Cleared when H/W reset or S/W reset. 0: Disable Preliminary V.10 Oct.07,1999 295 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1: Enable When CODEC_PD = 1, BCLK keeps low, a rising edge of ACDI1 will set WAVE_EV to high 3 R/W (AC_PM_EN_) Analog CODEC Power Management Enable 0: Enable If enabled, AC97 bit clock can be shut off according to PM_ST 1: Disable 2 R/W (DC_RST) Digital Controller Software Reset 0:normal 1:Reset Digital Controller 1 R/W (DC_PM_EN_) Digital Controller Power Management Enable 0:Enable When enabled, the internal pci clock can be shut off or turn on according to PM_ST. 1:Disable 0 R/W (DCC_EN) 0:Disable Dynamic Clock Control Enable
1:Enable. CLKRUN# scheme will be enabled. Register 47h Inactivity Timer Expiration Control Default Value: 00h Access: Read /Write Bit 7:0 Access R/W Description Inactivity timer expiration base (in second ) Every time when audio engine enters into D2 state, the Inactivity timer will load the base count from this register and start counting at 1s clock rate. When the MSB of the counter goes from high to low, the timer expired. When not at D2 state, the timer is reset. Register 48h INT Acknowledge Snoop Register: Default Value: 00h Access: Read /Write Bit 15:7 Access R/W Description (INT_VEC) Interrupt Vector to be matched 296 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 R/W (INTA_SNOOP_ENA) Enable bit. 0:Disable 1:Enable Register DCh Power Management Capability Register (PMC) Default Value: E6110001h Access: Read Only Bit 7:0 15:8 31:16 31:27 26 25 24:22 21 20 19 18:16 Access RO RO RO RO RO RO RO RO RO RO RO Description (PM_Cap_ID) Power management capability identifier , read only as 01h (PM_Next_Ptr) Next data structure item list pointer in the PCI header, read only as 00h (PM_CAP) Power management capability register, read only as E611h. (PME_Support) PME# supported PM_ST, read only as 01100b, indicates that PME# can be asserted in D2, D3hot. (D2_Support) Read only as 1, indicates D2 supported. (D1_Support) Read only as 1, indicates D1 supported. Reserved. Read only as 000b (DSI) Device Specific Initialization. Read only as 0. (Vaux) Auxiliary Power Source. Read only as 0. (PME_clk) PME clock. Read only as 0, indicates that no PCI clock is required to generate PME#. (Version)Read only as 001b, indicates PPMI v1.0 compliance Interrupt Acknowledge Snooping
Register E0h Power Management Control/Status Register (PMCSR) & PMCSR_BSE & Data: Default Value: 00000000h Access: Read /Write Bit 31:24 23:16 15:0 Access R/W R/W R/W (Data) Read only as 00h. (PMCSR_BSE) Read only as 00h. (PMCSR) Power Management Control/Status Register 297 Silicon Integrated Systems Corporation Description
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 15 R/W (PME_Status) Read/Write-Clear. 0:(Default) Normal (PME# is controlled by bit[8] PME_En) 1:PME# can be asserted independent of bit[8] (PME_En). Writing 0 to this bit has no effectt. Writing 1 to this bit will clear this bit, and also cause the chip to stop asserting PME#. 14:13 12:9 8 R/W R/W R/W (Data_Scale) Read only as 00b.
(Data_Select) Read only as 0000b (PME_En) Read/Write.
0: (Default) PME# is disabled to be asserted. 1:PME# is enabled to be asserted. 7:2 1:0 R/W R/W Reserved. Read only as 000000b (PM_ST) Power State. Read/Write. Read will return current Power State, write will set to new state. 00 01 10 11 D0 D1 D2 D3hot
14.2
Operational Registers
Access R/W R/W R/W R/W R/W R/W 298 Mnemonic Register Legacy DMA Playback Buffer Base Register Port 1 Legacy DMA Playback Buffer Base Register Port 2 Legacy DMA Playback Buffer Base Register Port 3 Legacy DMA Playback Buffer Base Register Port4 Legacy DMA Playback Byte Count Register 1 Legacy DMA Playback Byte Count Register 2 Silicon Integrated Systems Corporation
Operation. Offset 00h 01h 02h 03h 04h 05h Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 06h 07h 08h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 1A or 1Bh 1C or 1Dh 1Eh 1Fh 40-43h 44-47h 48-4Bh 4C-4Fh R/W R/W RO WO R/W WO WO WO WO R/W R/W R/W R/W R/W R/W WO RO R/W RO RO R/W R/W R/W R/W Legacy DMA Playback Byte Count Register 3 Legacy DMA Playback Misc. Register Legacy DMA Controller Command / Status Register Legacy DMA Single Channel Mask Port Legacy DMA Register Channel Operation Mode
Legacy DMA Controller First_Last Flag Clear Port Legacy DMA Controller Master Clear Port Legacy DMA Controller Clear Mask Port Legacy DMA Controller Multi-Channel Mask Register Legacy FmMusic Bank 0 Register Index / Legacy FmMusic Status Legacy FmMusic Bank 0 Register Data Port Legacy FmMusic Bank 1 Register Index Legacy FmMusic Bank 1 Register Data Port Legacy Sound Blaster Mixer Register Index Legacy Sound Blaster Mixer Register Data Port Legacy Sound Blaster ESP Reset Port Legacy Sound Blaster ESP Data Port Legacy Sound Blaster Command / Status Port Legacy Sound Blaster ESP Data Ready / IRQ Acknowledge Port 1 Legacy Sound Blaster ESP Data Ready / IRQ Acknowledge Port 2 AC-97 Mixer Write Register AC-97 Mixer Read Register Serial Interface Control Register AC97 General Purpose IO Register
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 50-53h 54-55h 56h 58-5Bh 5Ch 5Eh 5Fh 60-63h 70-73h 7C-7Fh 80-83h 84-87h 88-8Bh 8C-8Fh 90-93h 94-97h 98-9Bh 9C-9Fh A0-A3h A4-A7h A8-ABh AC-AFh B0-B3h B4-B7h B8-BBh Preliminary V.10 Oct.07,1999 RO RO RO R/W RO R/W R/W RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 300 SiSAudio Status Register Legacy Sound Blaster Frequency Read Back Register Legacy Sound Blaster Time Constant Read Back Register SiSAudio Scratch Register SiSAudio Version Control Register SB ESP Version High Byte Control Register SB ESP Version Low Byte Control Register OPL3 Emulation Channel Key on/off Trace Register S/PDIF Channel Status Register General purpose IO Register START command and status register for Bank A Channel STOP command and status register for Bank A Delay flag of Bank A Sign bit of CSO Bank A Current Sample Position Flag Current Envelope Buffer Control Bank A address engine interrupt Envelope engine interrupt register Global Control & Channel Index Bank A Address Engine Interrupt Enable Global Music Volume & Global Wave Volume Sample Change Step for Legacy Playback & Recording Miscellaneous Int & Status START command and status register for Bank B Channel STOP command and status register Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset for Bank B BC-BFh C0-C3h C4-C7h C8-CBh CC-CFh D0-D3h D8-DBh DC-DFh E0-E3h E4-E7h E8-EBh EC-EFh RO R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W Bank B Current Sample Position Flag Sound Blaster Base Block Length & Current Block Length Sound Blaster Control Playback Sample Timer Bank B Low Frequency Oscillator Control Sample Timer Target Bank B address engine interrupt Bank B Address Engine Interrupt Enable CSO & ALPHA & FMS LBA ESO & DELTA For Bank A: LFO_CTRL & LFO_CT & FMC & RVOL & CVOL For Bank B: Bank B ATTRIBUTE & FMC & RVOL & CVOL F0-F3h R/W For Bank A: Bank A GVSEL & PAN & VOL & CTRL & Ec For Bank B: Bank B GVSEL & PAN & VOL & CTRL & Bank A LFO_INIT F4h F8h EBUF1 EBUF2
Register 0h DMAR0 ( Legacy DMA Playback Buffer Base Register Port 1) Legacy Address: DDMASlaveBase + 0h || 0000h / 0002h Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description Legacy DMA Playback Buffer Current Transfer Address 7-0 The PCI bus interface circuit should response to I/O read to 0000h or 0002h on the PCI bus only when DMASnoopEn is active
Write: Legacy DMA Playback Buffer Base Address 7-0 Preliminary V.10 Oct.07,1999 301 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Read: Legacy DMA Playback Buffer Current Transfer Address 70 Register: 1h DMAR1 (Legacy DMA Playback Buffer Base Register Port 2) Legacy Address: DDMASlaveBase + 1h || 0000h / 0002h Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description Legacy DMA Playback Buffer Current Transfer Address 15-8 The PCI bus interface circuit should response to I/O read to 0000h or 0002h on the PCI bus only when DMASnoopEn is active
Write: Legacy DMA Playback Buffer Base Address 15-8 Read: Legacy DMA Playback Buffer Current Transfer Address 15-8 Register: 2h DMAR2 ( Legacy DMA Playback Buffer Base Register Port 3) Legacy Address: DDMASlaveBase + 2h || 0087h / 0083h Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description Legacy DMA Playback Buffer Current Transfer Address 23-16 The PCI bus interface circuit should response to I/O read to 0087h or 0083h on the PCI bus only when DMASnoopEn is active Write: Legacy DMA Playback Buffer Base Address 23-16 Read: Legacy DMA Playback Buffer Current Transfer Address 23-16 Register: 3h DMAR3 ( Legacy DMA Playback Buffer Base Register Port4) Legacy Address: DDMASlaveBase + 3h Default Value: 00h
Access: Read/Write
Bit 7:0 Access R/W Description Legacy DMA Playback Buffer Current Transfer Address 31-24 Write: Legacy DMA Playback Buffer Base Address 31-24 Read: Legacy DMA Playback Buffer Current Transfer Address Preliminary V.10 Oct.07,1999 302 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31-24 This register is intended for system which has DDMA Master. Any time when legacy DMA playback is not running, this register must be reset to 0 by software driver. Register: 4h DMAR4 ( Legacy DMA Playback Byte Count Register 1) Legacy Address: DDMASlaveBase + 4h || 0001h / 0003h Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description Legacy DMA Playback Current Byte Count 7-0 The PCI bus interface circuit should response to I/O read to 0003h or 0001h on the PCI bus only when DMASnoopEn is active Write: Legacy DMA Playback Byte Base Count 7-0 Read: Legacy DMA Playback Current Byte Count 7-0 Register: 5h DMAR5 (Legacy DMA Playback Byte Count Register 2) Legacy Address: DDMASlaveBase + 5h || 0001h / 0003h Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description Legacy DMA Playback Current Byte Count 15-8 The PCI bus interface circuit should response to I/O read to 0003h or 0001h on the PCI bus only when DMASnoopEn is active. Write: Legacy DMA Playback Byte Base Count 15-8 Read: Legacy DMA Playback Current Byte Count 15-8 Register: 6h DMAR6 (Legacy DMA Playback Byte Count Register 3) Legacy Address: DDMASlaveBase + 6h Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description Legacy DMA Playback Current Byte Count 23-16 Write: Legacy DMA Playback Byte Base Count 23-16 Read: Legacy DMA Playback Current Byte Count 23-16
Preliminary V.10 Oct.07,1999
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Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset This register is intended for system which has DDMA Master. Any time when legacy DMA playback is not running, this register must be reset to 0 by software driver. Register: 7h DMAR7(Legacy DMA Playback Misc. Register) Legacy Address: DDMASlaveBase + 7h Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description This Register is for internal debugging use.
Register: 8h DMAR8(Legacy DMA Controller Command / Status Register) Legacy Address: DDMASlaveBase + 8h || 0008h Default Value: 00h Access: Read Only Bit 7:0 Access RO Description Status register for implemented legacy 8237-A DMA channel. Implementation of this register maintains the compatibility with legacy 8237-A status register. However, when reading this register, the return value should be different for I/O read to (DDMASlaveBase + 8h) , I/O read to (AudioBase +8h)and I/O read to (0008h). I/O read to (DDMASlaveBase + 08h) is normally initiated by DDMA Master. I/O read to (AudioBase + 08h) is normally initiated by our debug program. The DDMA Master will take the responsibility to combine the return value of each DMA Slave Channel in the system and return the final resultant byte to response to the PCI I/O read to 0008h initiated by Host. The PCI bus interface circuit should response to I/O read to 0008h on the PCI bus only when DMASnoopEn is active. Register: Ah DMAR10(Legacy DMA Single Channel Mask Port) Legacy Address: 000Ah Default Value: 00h Access: Write Only Bit 0 Access WO Description Channel mask register for implemented legacy 8237-A DMA channel. Writing to this register will affect the legacy DMA operation of SiSAudio, implementation of this register maintains the register compatibility with legacy 8237-A DMA signal channel mask register. For system which has DDMA Master, it is the DMA Master' s responsibility to update the legacy channel mask bit 304 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset DMAR15.0 with address (DMASlaveBase + Fh) when a I/O write to 000Ah occurred on PCI Bus. When snooping legacy 8237-A register operation is enabled, any I/O write to 000Ah should be snooped to DMAR15.0 if the channel number matches the snooping legacy DMA channel number. Register: 0Bh DMAR11(Legacy DMA Channel Operation Mode Register) Legacy Address: DDMASlaveBase + 0Bh || 000Bh Default Value: 00h Access: Read / Write Bit 7:0 Access R/W Description This register can only be read out through AudioBase + 0Bh port channel mode register for implemented legacy 8237-A DMA channel. Writing to this register will affect the legacy DMA operation of SiSAudio , implementation of this register maintains the register compatibility with legacy 8237-A DMA channel mode register for system with or without DDMA Master . For system which has DDMA Master, it is the DMA Master' s responsibility to update this register when a I/O write to 000Bh occurred on PCI Bus. When snooping legacy 8237-A register operation is enabled, any I/O write to 000Bh should be snooped to this register if the channel number matches the snooping legacy DMA channel number.
Register: Ch DMAR12(Legacy DMA Controller First_Last Flag Clear Port) Legacy Address: 000Ch Default Value: Access: Write Only Bit 0 Access WO Description First_Last flag clear register for implemented legacy 8237-A DMA channel . Writing to this register will clear the flag signal First_Last. Implementation of this register maintains the register compatibility with legacy 8237-A DMA controller for system without DDMA Master. For system which has DDMA Master, it is the DMA Master' s responsibility to implement this flag. When snooping legacy 8237-A register operation is enabled, any I/O write to 000Ch should clear First_Last flag Register: Dh DMAR13(Legacy DMA Controller Master Clear Port) Legacy Address: DDMASlaveBase + 0Dh || 000Dh Default Value: Preliminary V.10 Oct.07,1999 305 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Access: Bit 0 Write Only Access WO Description Master clear register for implemented legacy 8237-A DMA channel . Writing to this register has the effect of hardware reset to the implemented legacy 8237-A DMA channel. Implementation of this register maintains the register compatibility with legacy 8237-A DMA controller for system with or without DDMA Master. For system which has DDMA Master, it is the DMA Master' s responsibility to write to this register when a write to legacy 8237A master clear register (I/O write to 000Dh) is on the PCI Bus. When snooping legacy 8237-A register operation is enabled, any I/O write to 000Dh should clear several legacy flags such as First_Last flag. Register: Eh DMAR14( Legacy DMA Controller Clear Mask Port) Legacy Address: 000Eh Default Value: Access: Write Only Bit 0 Access WO Description Multi-channel mask clear port for implemented legacy 8237-A DMA channel . Writing to this register will affect the legacy DMA operation of SiSAudio , implementation of this register maintains the register compatibility with legacy 8237-A DMA multi-channel clear mask register . For system which has DDMA Master, it is the DMA Master' s responsibility to update the legacy channel mask bit DMAR15.0 with address (DMASlaveBase + Fh) when a I/O write to 000Eh occurred on PCI Bus. When snooping legacy 8237-A register operation is enabled, any I/O write to 000Eh will reset DMAR15.0 to 0. Register: Fh DMAR15(Legacy DMA Controller Multi-Channel Mask Register) Legacy Address: DDMASlaveBase + 0Fh || 000Fh Default Value: 0b Access: Write Only Bit 1 Access WO Description Multi-channel mask register for implemented legacy 8237-A DMA channel . Implementation of this register maintains the register compatibility with legacy 8237-A DMA controller for system with or without Preliminary V.10 Oct.07,1999 306 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset DDMA Master. For system which has DDMA Master, it is the DMA Master' s responsibility to write DMAR15 when a write to legacy 8237-A multi-channel mask register (I/O write to 000Fh) is on the PCI Bus. When snooping legacy 8237-A register operation is enabled, any I/O write to 000Fh should update the mask flag for the implemented legacy 8237-A DMA channel. Register 10h SBR0 (Legacy FmMusic Bank 0 Register Index / Legacy FmMusic Status) Legacy Address: SBBase + 0h || SBBase + 8h || ADLIBBase + 0h Default Value: 00h Access: Read/Write Bit 7:0 Access RW Description 1:FmMusic Timer Interrupt Flag (Equal to Bit 6 + Bit 5) 1:FmMusic Timer 1 Overflowed Flag 1:FmMusic Timer2 Overflowed Flag 0:Reserved Legacy FmMusic Bank 0 Register Index Relative Internal Function Register File In order to emulate the legacy FmMusic(YMF262 or OPL3) function, a 512 bytes register file (RAM) must be implemented. By legacy access method, this register file has two banks and the bank index is specified by SBR0 and SBR2 respectively. This register file is byte-wide format , read/write RAM which has no high speed operation requirement. Relative Internal Functional Register Extracted From Legacy FmMusic Bank 0 Register File FmMusic-TIMER1 Bank Index : 02h Size : 8 bits Type : read/write Default : 00h 14.2.1 Bit 7..0 X Timer1 Preset Value If enabled Timer1 counter, it will increase every 1024 AC97 bit clock (12.288MHz) . When overflow occurs, this value is re-loaded into the counter. FmMusic-TIMER2 Bank Index : 03h Size : 8 bits Type : read/write Preliminary V.10 Oct.07,1999 307 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Default : 00h Bit 7..0 X Timer2 Preset Value If enabled Timer2 counter, it will increase every 4096 AC97 bitclock (12.288MHz). When overflow occurs, this value is re-loaded into the counter. FmMusic-Timer-CONTROL Bank Index : 04h Size : 8 bits Type : read/write Default : 00h Bit 7 1 Reset Bit 7-5 of Legacy FmMusic Status Register Bit 6 1 Reset Timer1 Overflow Flag Bit 5 1 Reset Timer2 Overflow Flag Bit 4-2 0 Reserved Bit 1 1 Enable Timer 2 14.2.2 Bit 0 1 Enable Timer 1 Bit 7-5 must be self-cleared to 0 after it is written as 1. When bit 1 or 0 is set from 0 to 1, the corresponding timer counter will load its preset value and start counting. When these bits are zero, the respective timer counter will stop counting. If bit 1 is set 1, bit 7 and 5 of FmMusic Status register will be set 1 when timer2 is overflowed. If bit 0 is set 1, bit 7 and 6 of FmMusic Status register will be set 1 when timer1 is overflowed. Register: 11h / 13h SBR1 (Legacy FmMusic Bank 0 Register Data Port) Legacy Address: SBBase + 1h || SBBase + 9h || ADLIBBase + 1h || SBBase + 3h || ADLIBBase + 3h Default Value: XXh Access: read/write Bit 7:0 Access R/W Description Legacy FmMusic Bank 0 Register(indexed by SBR0) Data
When writing to this register, if SBR0 is B0h-B8h and bit 5 of the content (indexed by SBR0) is changed from 0 to 1 or vice versa, or SBR0 is BDh and any one of bit 4-0 of the content (indexed by SBR0) is changed from 0 to 1 or vice versa, an OPL3 Bank0 Key On/Off Dirty Flag will be set at SiSAudio Status Register ASR0 and AOPLSR0. Register: 12h SBR2 (Legacy FmMusic Bank 1 Register Index) Legacy Address: SBBase + 2h || ADLIBBase + 2h Default Value: 00h Access: read/write Bit Access 308 Description Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:0 R/W Legacy FmMusic Bank 1 Register Index SBR3 (Legacy FmMusic Bank 1 Register Data Port)
Register: 11h / 13h
Legacy Address: SBBase + 1h || ADLIBBase + 1h || SBBase + 3h || ADLIBBase + 3h Default Value: XXh Access: read/write Bit 7:0 Access R/W Description Legacy FmMusic Bank 1 Register(indexed by SBR2) Data
When write to this register, if SBR2 is B0h-B8h and bit 5 of the content (indexed by SBR2) is changed from 0 to 1 or vice versa, an OPL3 Bank1 Key On/Off Dirty Flag will be set at SiSAudio Status Register ASR0 and AOPLSR0. Register: 14h SBR4 (Legacy Sound Blaster Mixer Register Index) Legacy Address: SBBase + 4h Default Value: 00h Access: read/write Bit 7:0 Access R/W Description Legacy SB16 / SBPRO Mixer Register Index
Register: 15h SBR5 (Legacy Sound Blaster Mixer Register Data Port) Legacy Address: SBBase + 5h Default Value: XXh Access: read/write Bit 7:0 Access R/W Description Legacy SB16 / SBPRO Mixer Register (indexed by SBR4) Data Port
Register: 16h / 17h SBR6 (Legacy Sound Blaster ESP Reset Port) Legacy Address: SBBase + 6h || SBBase + 7h Default Value: Access: write only Bit 0 Access WO Description 1:Enter Legacy SB16 / SBPRO ESP Reset State 0:Escape From SB16 / SBPRO ESP Reset State ESP Reset should do the following things: a. Reset ESP to no operation status and clear ESP Busy Flag. b. Stop wave engine SB channel operation. Preliminary V.10 Oct.07,1999 309 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Reset any flags that may affect the next command execution. Register: 1Ah / 1Bh SBR7 (Legacy Sound Blaster ESP Data Port) Legacy Address: SBBase + Ah || SBBase + Bh Default Value: 00h Access: Read only Bit 7:0 Access RO Description Data returned by Legacy SB16 / SBPRO ESP Read Operation
Register: 1Ch / 1Dh SBR8 (Legacy Sound Blaster Command / Status Port) Legacy Address: SBBase + Ch || SBBase + Dh Default Value: 00h Access: read/write Bit 7:0 7 Access WO RO Description The Command (Operator) or Data (Operand ) Written to Legacy SB ESP 0:Legacy SB ESP is Available For Next Command / Data 1:Legacy SB ESP is Busy. 6:0 RO Reserved
After the command / data has been written to the ESP Command / DATA port, bit 7 of this status register will be set to 1 (busy) . After ESP has processed the written command / data and waiting for the next one , bit 7 of this status register will be reset to 0 (not busy). Any acknowledge byte must be readback before any new command is issued. ESP will be set busy after this port has ever been written and will be set not busy if the command/status has been read four times. Register: 1Eh SBR9 (Legacy Sound Blaster ESP Data Ready / IRQ Acknowledge Port 1) Legacy Address: SBBase + Eh Default Value: 00h Access: read only Bit 7 Access RO Description 0:Data is not available on SBR7. 1:Data is available on SBR7. 6:0 RO Reserved
Reading this register will clear the interrupt generated by the ESP for NON-BX type legacy SB DMA command. After SBR7 has been read, bit 7 of this register will reset to 0 (no data) until the next read data is available and set bit 7 of this register. Preliminary V.10 Oct.07,1999 310 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register: 1Fh SBR10 (Legacy Sound Blaster ESP Data Ready / IRQ Acknowledge Port 2 Legacy Address: SBBase + Fh Default Value: 00h Access: Read only Bit 7 Access RO Description 0:Data is not available on SBR7. 1:Data is available on SBR7. 6:0 RO Reserved
Reading this register will clear the interrupt generated by the ESP for BX type legacy SB DMA command. After SBR7 has been read, bit 7 of this register will reset to 0 (no data) . If the next read data is available at SBR7, bit 7 of this register will again be set to 1. Register 40h ACWR(AC-97 Mixer Write Register) Default Value: : 00000000h Access: Read /Write Bit 31:16 15 Access R/W R/W Description Data to be written into AC-97 mixer register; Read: 0:ready to write AC-97 mixer register 1:busy writing AC-97 mixer (indexed by Bit 7..0); Write: 0:do nothing 1:write AC-97 mixer register (indexed by bit 7..0) with bit 31-16; Audio_Write_Busy: indicating Audio driver is busy writing AC97. Write 0 to clear. Write 1: if bit 13 = 0, this bit can be set, else do nothing. Read 0: fail to set Audio_Write_Busy. 1: succeed to set Audio_Write_Busy. Modem_Write_Busy: indicating Modem driver is busy writing AC97. Write : If BSModem enabled, do nothing, else clear this bit. Read 1: indicating Modem driver is busy writing AC97. Read 0: Modem driver is not busy writing AC97. Reserved index of the AC-97 mixer register to be written; index of the AC-97 mixer register to be written; Preliminary V.10 Oct.07,1999 311 Silicon Integrated Systems Corporation
14
R/W
13
RO
12:8 7:0
R/W R/W
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bit 7=0 Bit 7=1 for Primary CODEC; for Secondary CODEC.
Register 44h ACRD(AC-97 Mixer Read Register) Default Value: 00000000h Access: Read /Write Bit 31:16 Access R/W Reserved 15 R/W 0:bit 31..16 is valid data of AC-97 mixer register (indexed by bit 7..0) 1:busy reading AC-97 mixer register (indexed by bit 7..0); 0:do nothing 1:read AC-97 mixer register (indexed by bit 7..0) to bit 31..16; Audio_Read_Busy: indicating Audio driver is busy reading AC97. Write 0 to clear. Write 1: if bit 13 = 0, this bit can be set, else do nothing. Read 0: fail to set Audio_Read_Busy. 1: succeed to set Audio_Read_Busy. Modem_Read_Busy: indicating Modem driver is busy reading AC97. Write : If BSModem enabled, do nothing, else clear this bit. Read 1: indicating Modem driver is busy reading AC97. Read 0: Modem driver is not busy reading AC97. Reserved index of the AC-97 mixer register to be read; index of the AC-97 mixer register to be read; Bit 7=0 Bit 7=1 for Primary CODEC; for Secondary CODEC. Description AC-97 mixer register contents
14
R/W
13
RO
12:8 7:0
R/W R/W
Register 48h SCTRL (Serial INTF Control Register) Default Value: 00014000h Access: Read /Write Bit 26 Access RO 0:Normal Preliminary V.10 Oct.07,1999 312 Silicon Integrated Systems Corporation Description CODEC Power Down State flag
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1: CODEC is in power down mode When PM_ST enters D3, this bit will be set. 25 RO Secondary CODEC Ready flag 0: Not ready 1: Ready 24 RO Primary CODEC Ready flag 0: Not ready 1: Ready 23 R/W GPIOOUT Slot Enable 0: Disable 1: Enable (If DBLRATE_EN is 0) HSETOUT Slot Enable 0: Disable 1: Enable (If DBLRATE_EN is 0) 21 R/W LINE2OUT Slot Enable 0: Disable 1: Enable (If DBLRATE_EN is 0) 20 R/W LINE1OUT Slot Enable 0: Disable 1: Enable 19 R/W LFEOUT Slot Enable 0: Disable 1: Enable 18 R/W CENTEROUT Slot Enable 0: Disable 1: Enable 17 R/W SURROUT L/R Slot Enable 0: Disable 1: Enable PCMOUT L/R Slot Enable, Default: 1 0: Disable 1: Enable (Default) 15:14 R/W Secondary CODEC ID Default: Preliminary V.10 Oct.07,1999 01 313 Silicon Integrated Systems Corporation
22
R/W
16
R/W
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 13 R/W GPIOIN Slot Select 0: Primary CODEC GPIOIN slot input to GPIOIN buffer 1: Secondary CODEC GPIOIN slot input to GPIOIN buffer 12 R/W HSETIN Slot Select 0: Primary CODEC HSETIN slot input to HSETIN buffer 1: Secondary CODEC HSETIN slot input to HSETIN buffer 11 R/W LINE2IN Slot Select 0: Primary CODEC LINE2IN slot input to LINE2IN buffer 1: Secondary CODEC LINE2IN slot input to LINE2IN buffer 10 R/W MIC Slot Select 0: Primary CODEC MIC slot input to MIC buffer 1: Secondary CODEC MIC slot input to MIC buffer LINE1IN Slot Select 0: Primary CODEC LINE1IN slot input to LINE1IN buffer 1: Secondary CODEC LINE1IN slot input to LINE1IN buffer 8 R/W PCMIN Slot Select 0: Primary CODEC PCMIN slot input to PCMIN_A buffer 1: Secondary CODEC PCMIN slot input to PCMIN_A buffer 7 R/W I2S Input Function Enable 0: Disable If disabled, the clocks of I2S receiver should be shut down. 1: Enable 6 R/W I2S Output Function Enable 0: Disable If disabled, the clocks of I2S transmitter should be shut down. 1: Enable 5 R/W S/PDIF Output Function Enable 0:Disable If disabled, the clocks of SPDIF transmitter should be shut down. 1: Enable 4 R/W CODEC Double Rate Enable 0: Disable 1: Enable PCM Output Select (Primary/Secondary) 314 Silicon Integrated Systems Corporation
9
R/W
3
R/W
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0: PCM Output up to Primary CODEC request 1: PCM Output up to Secondary CODEC request 2 R/W MCLK clock rate select for I2S Output 0: MCLK = 12.288M 1: MCLK = 6.144M 1 R/W CODEC Cold Reset Command 0: Normal 1: Cold Reset CODEC When write ` 1' to this bit, pin ACRST# should be driven to low for at least 1us. After Power up, this bit will set to issue AC97 cold reset, SW must write 0 to stop issuing AC97 cold reset. 0 R/W CODEC Warm Reset Command 0: Normal 1: Warm Reset CODEC When write ` 1' to this bit, pin ACSYNC should be driven to high for at least 1us. Register 4Ch ACGPIO (AC97 General Purpose IO Register) Default Value: 00000000h Access: Read /Write Bit 31:16 15 Access R/W R/W Description data to be written into AC-97 through output Slot 12; This bit is status when read. 0:ready to output AC-97 Slot 12 1:busy This bit is command when write 0:do nothing 1:output AC-97 Slot 12 14:5 4 R/W R/W Reserved Secondary CODEC GPIO_INT Enable 0:Disable 1:Enable 3 R/W Primary CODEC GPIO_INT Enable 0:Disable Preliminary V.10 Oct.07,1999 315 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1:Enable 2 R/W Secondary CODEC GPIO_INT register This bit will be updated with Secondary input Slot 12 bit 0 of every AC97 frame. 1 R/W Primary CODEC GPIO_INT register This bit will be updated with Primary input Slot 12 bit 0 of every AC97 frame. 0 R/W Reserved
Register 50h ASR0 (SiSAudio Status Register) Default Value: 00000000h Access: Read Only Bit 31:30 29 Access RO RO Description Reserved Read/Write, MPU401 Output Buffer Select 0: 8-byte 1: 128-byte Legacy Recording IRQ MASK 0:Generate IRQ when legacy recording block length expired. 1:Don' t generate IRQ when legacy recording block length expired 1:SB ESP is at special DMA mode 00:SB ESP is at get operator state 01:SB ESP is at get first operand state 11:SB ESP is at get second operand state 10:SB ESP is at get third operand state 1:SB Mixer Soft-Reset 1:SB PRO Command Captured Most Recently (Non-Bx or Cx Type Command Captured) 1:SB16 Command Captured Most Recently (Bx or Cx Type Command Captured) 1:SB Engine Sample Rate Set By Frequency Most Recently 1:SB Engine Sample Rate Set By Time Constant Most Recently 1:SB16 Mixer Register Update 1:SB PRO Mixer Register Update 1:OPL3 Bank1 Key On/Off 1:OPL3 Bank0 Key On/Off 316 Silicon Integrated Systems Corporation
28
RO
27 26:25
RO RO
24 23 22 21 20 19 18 17 16
RO RO RO RO RO RO RO RO RO
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 15 14 13 12 11 10 9:8 RO RO RO RO RO RO RO 0:AC-97 codec is not ready 1:AC-97 codec is ready 0:SB Mixer Register MX0E.1 is 0 1:SB Mixer Register MX0E.1 is 1 0:SB ESP is not at Direct Recording Mode 1:SB ESP is at Direct Recording Mode 0:SB ESP has no ack byte 1:SB ESP has ack byte that needs to be read out 0:SB ESP DMA Command is not valid 1:SB ESP DMA command is valid 0:SB ESP Engine at Digital Audio Off State 1:SB ESP Engine at Digital Audio On State 00:SB ESP Engine Command Port Not Busy 01:SB ESP Engine Command Port Busy 10:SB ESP DMA Test Busy 11:SB ESP Command Buffer Full 0:8 bit data format 1:16 bit data format 0:mono 1:stereo 0:unsigned data format 1:signed data format 0:playback 1:recording 0:SB DMA loop disable 1:SB DMA loop enable LegacyCMD 000 Digital Mixer 001 stop run : No any operation. No contribution to : Normal operation.
7 6 5 4 3 2:0
RO RO RO RO RO RO
010 silent_DMA : SBCL will count; CA, CBC won' t count. No data fetching. No interpolation. No contribution to Digital Mixer 011 reserve
100 silent_SB : SBCL, CA & CBC will count as the same as run mode.No data fetching. No interpolation. No Preliminary V.10 Oct.07,1999 317 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset contribution to Digital Mixer 101 pause: SBCL, CA & CBC don' t change.
let SBALPHA unchanged, CACHE_HIT=1 drive current LD (or LD_L, LD_R) to Digital Mixer 110 111 reserve direct play : SBCL, CA & CBC don' t change.
drive SBDD to Digital Mixer Only one bit of Bit 21 and Bit 20 can be set 1 by implemented SB ESP Engine at any time. Only one bit of Bit 23 and Bit 22 can be set 1 by implemented SB ESP Engine at any time. Register 54h ASR1 (Legacy Sound Blaster Frequency Read Back Register) Default Value: 00h Access: Read Only Bit 15:0 Access RO Description Sample Frequency Set by SB Command 41h or 42h
Register 56h ASR2 (Legacy Sound Blaster Time Constant Read Back Register) Default Value: 00h Access: Read Only Bit 7:0 Access RO Description Time Constant Value Set by SB Command 40h
Register 58h ASR3 ( SiSAudio Scratch Register ) Default Value: 00000000h Access: Read / Write Bit 31:0 Access R/W Description
Register 5ch ASR4 (SiSAudio Version Control Register) Default Value: 88h Access: Read Only Bit 7:0 Access RO Description
Register 5Eh ASR5 (SB ESP Version High Byte Control Register) Default Value: 4h Access: Read /Write Preliminary V.10 Oct.07,1999 318 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Bit 3:0 Access R/W Description
Register 5Fh ASR6 (SB ESP Version Low Byte Control Register) Default Value: 2h Access: Read / Write Bit 3:0 Access R/W Description
Register 60h AOPLSR0 (OPL3 Emulation Channel Key on/off Trace Register) Default Value: 00000000h Access: Read Only Bit 31:25 24:16 15 Access RO RO RO Description Reserved Bank1 channel 8-0 key on/off event captured Read only 0:Bank0 1:Bank1 14 13:9 8:0 RO RO RO Reserved 1:OPL3 rhythm channel 4-0 key on/off event captured 1:Bank0 channel 8- 0 key on/off event captured.
All the flag will be cleared after this register is read. Register 70h SPDIF_CS (S/PDIF Channel Status Register) Default Value: 02000000h Access: Read/Write Bit 31:30 Access R/W Description Reserved Hardwired to 00b 29:28 R/W Clock Accuracy Read/Write, Default: 00b 27:24 R/W Sample rate Read/Write, Default: 2h (48kHz) 23:20 R/W Read/Write, Default: 0h
Preliminary V.10 Oct.07,1999
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Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 19:16 15:8 7:6 5:3 2 R/W R/W R/W R/W R/W Read/Write, Default: 0h Read/Write, Default: 00h Read/Write, Default: 00b Read/Write, Default: 000b Copyright Read/Write, Default: 00b 1 R/W Audio content flag Read/Write, Default: 0 0 R/W Professional flag Read/Write, Default: 0 Register 7Ch GPIO(General purpose IO Register) Default Value: 00000000h Access: Read /Write Bit 31:24 23:16 15:10 9 8 7:1 Access R/W R/W R/W R/W R/W R/W RO reserved reserved GPO[7:2] Set to indicate BSModem that SiSAudio has issued AC97 power down command. After Audio driver has initialized AC97, it must set this bit to inform BSModem. GPI[7:1] Read 1 indicating that BSModem has initialized AC97. Description
All reserved bits return 0 when read. 14.2.3 Wave Engine Register: 64 voice channels are classified into two banks. * Bank A: channel 0-31 (optimized for MIDI) * Bank B: channel 32-63 (optimized for Wave, WDM Stream, DirectX buffer, I2S, S/PDIF, MODEM, Handset, Recording, Microphone, Main Mixer Capture, Reverb Send, Chorus Send, AC97 SURR, AC97 CENTER/LFE) * Each channel in Bank A can only be programmed as a playback channel with individual EM(envelope modulation), individual LFO AM and individual LFO FM. Preliminary V.10 Oct.07,1999 320 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
Channels in Bank B have more flexibility. Each of them can be programmed as a Normal PB channel with global LFO AM and LFO FM but without EM, or as a Special PB channel, or as a REC channel, or as a REC_PB channel. Bit[31:19] of RegEC_B is Channel ATTRIBUTE. Register 80h STAR_A (START command and status register for Bank A) Default Value: 00000000h Access: Read / Write Bit 31:0 Access R/W Description This register and STOP_A are used as Bank A channel start/stop command register when they are written, and used as Bank A channel running/stopped status register when they are read. bit n is for channel n. Reading from this I/O port will return the running/stopped status of Bank A 32 voice channels. 0:Stopped. When bit n is read as ` 0' , it means any operation of channel n, including address generation, sample data fetching, interpolation, and envelope calculation is stopped. And this channel has no contribution to the digital mixer. This bit will be reset from ` 1' to ` 0 in four cases. ' when a ` 1' is written to the corresponding bit in register STOP_A . when out of data, i.e. when sample loop disabled and CSO (Current Sample Offset) >= ESO (End Sample Offset). when Ec (current envelope) drops down to -63.984375 dB. when current envelope buffer is in delay-stop mode, and EDLY count down to ` 0' . 1:Running. When bit n is read as ` 1' , it means channel n is working. This bit will be set from ` 0' to ` 1 only when a ` 1 is written to the ' ' corresponding bit in register START_A. Writing to this I/O port means issuing a start command to address engine and envelope engine in expected channel. 0:Ignore. A ` 0 written to bit n will not change the status of channel n. ' 1:Start. A ` 1 written to bit n will start channel n' s address engine and ' Preliminary V.10 Oct.07,1999 321 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset envelope engine and also set the status bit n to ` 1' . Register 84h STOP_A (Channel STOP command and status register for Bank A) Default Value: 00000000h Access: Read / Write Bit 31:0 Access R/W Description Reading from this I/O port will return the same value as from the last register START_A.
Writing to this I/O port means issuing a stop command to address engine and envelope engine in expected channel. 0:Ignore. A ` 0 written to bit n will not change the status of channel n. ' 1:Stop. A ` 1 written to bit n will stop channel n' s address engine and ' envelope engine, and also reset the corresponding status bit to `0 . ' Register 88h DLY (Delay flag of Bank A) Default Value: 00000000h Access: Read / Write Bit 31:0 Access R/W Description When read, this register will show the delay status of each channel of Bank A. Bit n is for channel n. 0:normal This bit will toggle from ` 1' to ` 0 when envelope engine change ' from a delay mode buffer to a non-delay mode buffer. When channel n is stopped, bit n will be reset to ` 0' . 1: channel is currently in delay mode (address engine keep stopped but envelope engine is running). This bit will toggle from ` 0' to ` 1 only when envelope engine begin ' to deal with a delay mode buffer. When write, 0:ignore (don' t change) 1:set to ` 1'
Preliminary V.10 Oct.07,1999
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Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 8Ch SIGN_CSO (Sign bit of CSO) (for Bank A only) Default Value: 00000000h Access: Read / Write Bit 31:0 Access R/W Description This register is used to store the sign bits of 32 channel' s CSO of Bank A, with ` 0' means current sample address is greater than or equal to LBA(Loop Begin Address), while ` 1' means current sample address is little than or equal to LBA. This register can be programmed with an initial status and will be updated by address engine. Write ` 0 :ignore (don' t change) ' Write ` 1 :set to ` 1' ' When channel n is stopped, bit n will be reset to ` 0' . Register 90h CSPF_A( Bank A Current Sample Position Flag) Default Value: 00000000h Access: Read only Bit 31:0 Access RO Description This register will show a flag which indicates the Bank A' s current sample is in a range between ESO/2 to ESO or in a range before ESO/2 (ESO is offset from loop begin to loop end). And this flag will be used for sample data double buffering control. Bit n is for channel n. 0:Before ESO/2 1:From ESO/2 to ESO WHEN CHANNEL N IS STOPPED, BIT N WILL BE RESET TO `0. ' Register 94h CEBC (Current Envelope Buffer Control) ( for Bank A only) Default Value: 00000000h Access: Read/Write Bit 31:0 Access R/W Description Reading from this register will return current envelope buffer flags of 32 channels of Bank A, which indicate currently envelope engine is using parameters from EBUF1 or EBUF2. Bit n is for channel n. 0:Buffer 1 1:Buffer 2 Writing ` 1 to bit n of this register will toggle the flag in channel n ' and force envelope engine to change buffer. Writing ` 0 to bit n ' Preliminary V.10 Oct.07,1999 323 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset won' t change anything in channel. 0:Ignore 1:Toggle When channel n is stopped, bit n will be reset to ` 0' . Register 98h AINT_A (Bank A address engine interrupt) Default Value: 00000000h Access: Read/Write Bit 31:0 Access R/W Description Any bits toggled from ` 0' to ` 1 will result in a IRQ. ' Reading from this I/O port will return the address INT status of Bank A' s 32 channels. Bit n is for channel n. 0:No INT 1:INT This bit will be set in 2 cases: When CSO ( current sample offset ) >= ESO ( end sample offset ), and ENDLP_IE ( end of loop INT enable bit in Global Control register ) =1 and AINTEN_A bit n is set 1 for channel n. When CSO ( current sample offset ) >= ESO/2 ( middle of ESO ), and MIDLP_IE ( middle of loop INT enable bit in Global Control register ) =1 and AINTEN_A bit n is set 1 for channel n. Writing ` 1 to bit n of this register will reset this bit. ' 0:Ignore. A ` 0 written to bit n will not change the status of this bit. ' 1:reset A ` 1 written to bit n will reset this bit. ' Register 9Ch EINT( Envelope engine interrupt register) (for Bank A only) Default Value: 00000000h Access: Read/Write Bit 31:0 Access R/W Description Any bits toggled from ` 0' to ` 1 will result in a IRQ. ' Reading from this I/O port will return the envelope INT status of 32 channels of Bank A. Bit n is for channel n. Preliminary V.10 Oct.07,1999 324 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0:No INT 1:INT This bit will be set in 2 cases: When envelope buffer toggled, and ETOG_IE ( envelope toggle INT enable bit in Global Control register ) =1. When Ec ( current envelope ) <= FFFh ( -63.984375 dB ), and EDROP_IE ( envelope dropping to -63.984375dB INT enable bit in Global Control register ) =1. Writing ` 1 to bit n of this register will reset this bit. ' 0:Ignore. A ` 0 written to bit n will not change the status of this bit. ' 1: reset A ` 1 written to bit n will reset this bit. ' Register A0h GC & CIR ( Global Control & Channel Index) Default Value: 00000000h Access: Read/Write Bit 31:30 Access R/W Description are used to control Legacy Recording channel when record to mono sample. 00:left 01:right 10: (left+right+1)/2 11: Reserved. 29:28 R/W are IO 0008-read handling control bits. 00:never assert StatusRDY 01:StatusRDY = DMATCReached 10:StatusRDY = DMATCReached | LegacyDRQ 11:in this case, handshaking with StatusWR and manipulation of return byte should been done. StatusRDY keep ` 0 when initialization. ' If(StatusWR ==1) { StatusRDY = 1; if(DMAChannel==0) { ReturnByte[7:0] = {InputByte[7:5], DMAR8[4], InputByte[3:1], DMAR8[0]}; 325 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset } else { ReturnByte[7:0] = {InputByte[7:6], DMAR8[5], InputByte[4], InputByte[3:2], DMAR8[1], InputByte[0]}; } } if(DMASNOOPCS_==0 & ADR[7:0] = 8 & Data_rdy_ == 0 & StatusRDY==1) StatusRDY = 0; 27 R/W Test_loopback: This bit is used for wave engine loopback testing. 0:normal 1:force recording engine get new data from playback FIFO instead of aclink. 26 R/W Debugging Mode 0:Normal 1:Chip is in Debugging Mode. In Debugging Mode, 20 pins (including 8 pins of GPIO, 1 pin of SPDIF , 6 pins of I2S and 5 NC pins) are used as output to monitor 40 internal important signals. Detail in Appendix B. EXPROM Map Mode 00: 000h-1FFh of EXPROM is mapped to AudioMemBase 800h-FFFh low 16 bits; 800h-9FFh of EXPROM is mapped to AudioMemBase 800hFFFh high 16 bits; 01: 200h-3FFh of EXPROM is mapped to AudioMemBase 800h-FFFh low 16 bits; A00h-BFFh of EXPROM is mapped to AudioMemBase 800hFFFh high 16 bits; 10: 400h-5FFh of EXPROM is mapped to AudioMemBase 800h-FFFh low 16 bits; C00h-DFFh of EXPROM is mapped to AudioMemBase 800h-FFFh high 16 bits; 11: 600h-7FFh of EXPROM is mapped to AudioMemBase 800h-FFFh low 16 bits; E00h-FFFh of EXPROM is mapped to AudioMemBase 800h326 Silicon Integrated Systems Corporation
25:24
R/W
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset FFFh high 16 bits. 23 R/W EXPROM Dump Mode Enable 0:Disable 1:Enable If enabled, EXPROM(4096x12bit) is mapped to AudioMemBase according to bit[25:24], i.e. the content of EXPROM can be read out through AudioMem Read cycle. Test mode bits 00:normal mode (chip works normally in this mode) 01:test mode 1 10:test mode 2 11:test mode 3 The detail descriptions on test mode 1, 2, and 3 are given in Appendix B. Main Mixer Output Control 0:Main Mixer L/R a PCM L/R Output FIFO 1:Main Mixer L/R a MMC L/R Output Buffer S/PDIF Out Control 0 S/PDIF L/R Output Buffer a S/PDIF L/R transmitter 1:PCM L/R Output FIFO a S/PDIF L/R transmitter I2S Out Control 0:I2S L/R Output Buffer a I2S transmitter 1:SURR L/R Output FIFO a I2S transmitter PCMIN_B Mixing Enable/Disable 0:PCMIN_B Mixing Disable 1:PCMIN_B Mixing Enable Note: Controlled by PCMIN_SEL in Reg48h, either of Primary CODEC PCMIN slot or Secondary CODEC PCMIN slot will come into 3-level PCMIN_A buffer. And if PCMIN_B Mixing bit is enabled, the other slot will come into 1-level PCMIN_B buffer and will be mixed into Main Mixer. 64-Channel Mode 0:Legacy Mode 1:64 Channel Mode is INT enable bit for current envelope dropping to -63.984375dB. 0:disable 1:enable is INT enable bit for envelope buffer toggling. 327 Silicon Integrated Systems Corporation
22:21
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20
R/W
19
R/W
18
R/W
17
R/W
16
R/W
15
R/W
14
R/W
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0:disable 1:enable 13 R/W is INT enable bit for middle of loop. 0:disable 1:enable is INT enable bit for end of loop. 0:disable 1:enable is INT enable bit for playback underrun. 0:disable 1:enable When playback FIFO is empty, if this bit is set as ` 1' , a IRQ will be issued. is INT enable bit for recording overrun. 0:disable 1:enable When recording FIFO is full, if this bit is set as ` 1' , a IRQ will be issued. is Pause/Resume command bit. Read 0:Engine hasn' t been paused yet. 1:Engine has been paused already. Write 0:Resume Engine. 1:Pause Engine. When host writes ` 1' , this bit may not show ` 1' immediately. Engine will try to get paused as soon as possible. After engine has been paused already, this bit will be set to ` 1' . Once host writes ` 0' , this bit will be reset to ` 0' immediately and engine will work normally. is used to reset playback sample timer counter. When read , return 0;write 1 will reset STimer. is the channel index which is used to select a channel for access. 00h selects channel 0, 1Fh selects channel 31, 3Fh selects channel 63.
12
R/W
11
R/W
10
R/W
9
R/W
8 5:0
R/W R/W
All other bits are reserved. Register A4h AINTEN_A(Bank A Address Engine Interrupt Enable) Default Value: 00000000h Access: Read/Write Bit Access 328 Description Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31:0 R/W This register will control address engine interrupt for each channel of Bank A. Bit n is for channel n. 0:disable address engine interrupt for channel n 1:enable address engine interrupt for channel n Register A8h MUSICVOL & WAVEVOL(Global Music Volume & Global Wave Volume) Default Value: 00008080h Access: Read/Write Bit 31:24 Access R/W music right volume 0 FFh 23:16 R/W 0dB(no attenuation) -63.75dB(mute) Description
music left volume 0 0dB(no attenuation) FFh -63.75dB(mute) wave right volume 0 0dB(no attenuation) 80h -32dB (default) FFh -63.75dB(mute) wave left volume 0 0dB(no attenuation) 80h -32dB (default) FFh -63.75dB(mute)
15:8
R/W
7:0
R/W
Register Ach SBDELTA/DELTA_R (Sample Change Step for Legacy Playback & Recording) Default Value: 00000000h Access: Read/Write Bit 31:16 15:0 Access R/W R/W Reserved. SBDELTA: Fs/F48k in 4.12 format. SBDELTA_R: F48k/Fs in 4.12 format. Register B0h MISCINT (Miscellaneous Int & Status) Default Value: 00000000h Access: Read/Write Bit Access 329 Description Silicon Integrated Systems Corporation Description
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 24 R/W (ACGPIO_IRQ) is AC97 GPIO interrupt request. ACGPIO_IRQ = Reg4Ch[1] & Reg4Ch[3] | Reg4Ch[2] & Reg4Ch[4]. 23 R/W (ST_IRQ_En) is ST IRQ enable bit. 0:disable 1:enable (opltimer_ie) is OPL3 timer interrupt enable bit. 0:disable 1:enable (PB_24K_MODE) is playback 48k/24k mode control bit. 0:(default)Wave engine drives sample to CODEC at 48Khz 1:Wave engine drives sample to CODEC at 24Khz( in this mode, Delta should be programmed twice as that in 48Khz mode). (ST_TARGET_REACHED) is a flag with ` 1 indicates STIMER ' counter has been equal to ST_TARGET. This bit will be set to ` 1 once STIMER counter is equal to ' ST_TARGET. Write ` 1 will clear this bit. ' (mixer_overflow_flag) is a flag which indicates the result of mixer accumulator exceeds 7FFFFh. This bit will be set to ` 1 once accumulator overflows. ' Write ` 1 will clear this bit. ' (mixer_underflow_flag) is a flag which indicates the result of mixer accumulator is less than 80000h. This bit will be set to ` 1 once accumulator underflows. ' Write ` 1 will clear this bit. ' (REC_OVERUN) is recording overrun status bit. Active high. This bit will be set to ` 1 if recording is running & rec_req_ is active & ' data_rdy haven' t come. (PB_UNDERUN) is playback FIFO underrun status bit. Active high. This bit will be set to ` 1 if playback is running & FIFO is empty & f48 ' clock is coming. (ST_IRQ) is Sample Timer IRQ bit. Active high. Bit[7] = ST_IRQ_En | ST_TARGET_REACHED (ENVELOPE_IRQ) is Wave-table Envelope Engine IRQ bit. Active high. Bit[6] = | EINT[31:0] (ADDRESS_IRQ) is Wave-table Address Engine IRQ bit. Active 330 Silicon Integrated Systems Corporation
17
R/W
16
R/W
15
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7 6
R/W R/W
5
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Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset high. Bit[5] = ( | AINT_A[31:0] ) | ( | AINT_B[31:0] ) 4 3 2 1 0 R/W R/W R/W R/W R/W (OPL3_IRQ) is OPL3 timer IRQ bit. Active high. Bit[4] = timerirq & opltimer_ie (MPU401_IRQ) is MPU401 IRQ bit. Active high. Bit[3] = mpu401irq (signal from Legacy Audio block) (SB_IRQ) is sound blaster IRQ bit. Active high. Bit[2] = sbirq (signal from Legacy Audio block) (REC_OVERUN_IRQ) is recording overrun IRQ bit. Active high. Bit[1] = OVERUN_IE & Bit[9]. (PB_UNDERUN_IRQ) is playback FIFO underrun IRQ bit. Active high. Bit[0] = UNDERUN_IE & Bit[8].
All other bits are reserved bits. Register B4h STAR_B (START command and status register for Bank B) Default Value: 0000h Access: Read / Write Bit 31:0 Access R/W Description This register and STOP_B are used as Bank B channel start/stop command register when they are written, and used as Bank B channel running/stopped status register when they are read. bit n is for channel n. Reading from this I/O port will return the running/stopped status of Bank B 32 voice channels. 0:Stopped. When bit n is read as ` 0' , it means any operation of channel n, including address generation, sample data fetching, interpolation, and envelope calculation is stopped. And this channel has no contribution to the digital mixer. This bit will be reset from ` 1' to ` 0 ' in four cases. when a ` 1' is written to the corresponding bit in register STOP_B. when out of data, i.e. when sample loop disabled and CSO (Current Sample Offset) >= ESO (End Sample Offset). when Ec (current envelope) drops down to -63.984375 dB. when current envelope buffer is in delay-stop mode, and EDLY count down to ` 0' . 1:Running. Preliminary V.10 Oct.07,1999 331 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset When bit n is read as ` 1' , it means channel n is working. This bit will be set from ` 0' to ` 1 only when a ` 1 is written to the ' ' corresponding bit in register START_B. Writing to this I/O port means issuing a start command to address engine and envelope engine in expected channel. 0:Ignore. A ` 0 written to bit n will not change the status of channel n. ' 1:Start. A ` 1 written to bit n will start channel n' s address engine and ' envelope engine and also set the status bit n to ` 1' . Register B8h STOP_B (Channel STOP command and status register for Bank B) Default Value: 0000h Access: Read / Write Bit 31:0 Access R/W Description Reading from this I/O port will return the same value as from the last register START_B. Writing to this I/O port means issuing a stop command to address engine and envelope engine in expected channel. 0:Ignore. A ` 0 written to bit n will not change the status of channel n. ' 1:Stop. A ` 1 written to bit n will stop channel n' s address engine and ' envelope engine, and also reset the corresponding status bit to `0 . ' Register BCh CSPF_B( Bank B Current Sample Position Flag) Default Value: 00000000h Access: Read only Bit 31:0 Access RO Description This register will show a flag which indicates the Bank B' s current sample is in a range between ESO/2 to ESO or in a range before ESO/2 (ESO is offset from loop begin to loop end). And this flag will be used for sample data double buffering control. Bit n is for channel n. 0: Before ESO/2 1: From ESO/2 to ESO Preliminary V.10 Oct.07,1999 332 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset When channel n is stopped, bit n will be reset to ` 0' . Register C0h SBBL & SBCL (Sound Blaster Base Block Length & Current Block Length) Default Value: 00000000h Access: Read/Write Bit 31:0 Access R/W Description SBBL(Bit 31-16) is sound blaster base block length SBCL(Bit 15-0 ) is current value of sound blaster block length counter If sound blaster DMA loop is enabled(SBCTRL[3]=1), every time when SBCL changed from 0 to FFFFh, a INT will be issued, the contents of SBCL is reloaded from SBBL, and DMA operation continues . If sound blaster DMA loop is not enabled(SBCTRL[3]=0), every time when SBCL changed from 0 to FFFFh, a INT will be issued, the contents of SBCL is reloaded from SBBL, and set LegacyCMD to 101(pause). SBCTRL bit 7 is used to determine the counter operation mode (byte count or word count). The counter is a count down counter. Register C4h SBCTRL & SBE2R & SBDD (Sound Blaster Control) Default Value: 00000000h Access: Read/Write Bit 31:24 Access R/W Description is sound blaster DMA testing byte command data port(write only) Any time after Bit31-24 has ever been written, E2Status (source from wave engine) will be set high. E2Status will be cleared after the testing byte has been sent to the system location. is sound blaster direct mode playback data port is legacy sound blaster voice in/out control register 0:8 bit data format 1:16 bit data format 0:mono 1:stereo 0:unsigned data format 1:signed data format 0:playback 333 Silicon Integrated Systems Corporation
15:8 7:0 7 6 5 4
R/W R/W R/W R/W R/W R/W
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1:recording 3 R/W sound blaster DMA loop enable control 0:loop disabled. 1:loop enabled. LegacyCMD 000 stop : No any operation. No contribution to Digital Mixer 001 run : Normal operation. 010 silent_DMA : SBCL will count; CA, CBC won' t count. No data fetching. No interpolation. No contribution to Digital Mixer 011 reserve 100 silent_SB : SBCL, CA & CBC will count as the same as run mode. No data fetching. No interpolation. No contribution to Digital Mixer 101 pause : SBCL, CA & CBC don' t change. let SBALPHA unchanged, CACHE_HIT=1 drive current LD (or LD_L, LD_R) to Digital Mixer 110 reserve 111 Direct_playback : SBCL, CA & CBC don' t change. drive SBDD to Digital Mixer
2:0
R/W
Register C8h STimer (Playback Sample Timer) Default Value: 00000000h Access: Read only Bit 31:0 Access RO Description Bit 31-0 (STimer) will show current state of the sample timer counter which will count up every f48k clock and will be reset when RST_Stimer bit being written. Active high.
Register CCh LFO_B And I2S_DELTA (Bank B Low Frequency Oscillator Control) Default Value: 00000000h Access: Read/Write Bit 31:27 26:16 26 Access R/W R/W R/W Description Reserved - Read Only 00000b is used for Bank B LFO control (LFO_E_B) is Bank B LFO enable bit. 0:disabled 334 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1:enabled 25:24 R/W (LFO_R_B) is clock rate select of Bank B LFO counter. 00:LFO counter clock rate is 48kHz 01:LFO counter clock rate is 48kHz/4 10:LFO counter clock rate is 48kHz/16 11:LFO counter clock rate is 48kHz/64 (LFO_INIT_B)is the initial value of the Bank B LFO counter which will count down to 0 then reload. Reserved. (I2S_DELTA) (Read only) This register returns the autodetected DELTA of I2S input (fi2s/f48K).
23:16 15:13 12:0
R/W R/W R/W
Register D0h ST_TARGET (Sample Timer Target) Default Value: 00000000h Access: Read/Write Bit 31:0 Access R/W Description Bit 31-0 (ST_TARGET) is used to store a pre-set value. Once STIMER counter reaches that value, an IRQ called ST_IRQ will be issued if ST_IRQ_En = 1.
Register D8h AINT_B (Bank B address engine interrupt) Default Value: 00000000h Access: Read/Write Bit 31:0 Access R/W Description Any bits toggled from ` 0' to ` 1 will result in a IRQ. ' Reading from this I/O port will return the address INT status of Bank B' s 32 channels. Bit n is for channel n. 0:No INT 1:INT This bit will be set in 2 cases: When CSO ( current sample offset ) >= ESO ( end sample offset ), and ENDLP_IE ( end of loop INT enable bit in Global Control register ) =1 and AINTEN_B bit n is set 1 for channel n. When CSO ( current sample offset ) >= ESO/2 ( middle of ESO ), and MIDLP_IE ( middle of loop INT enable bit in Global Control register ) =1 and AINTEN_B bit n is set 1 for channel n. Preliminary V.10 Oct.07,1999 335 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Writing ` 1 to bit n of this register will reset this bit. ' 0:Ignore. A ` 0 written to bit n will not change the status of this bit. ' 1:reset A ` 1 written to bit n will reset this bit. ' Register DCh AINTEN_B(Bank B Address Engine Interrupt Enable) Default Value: 00000000h Access: Read/Write Bit 31:0 Access R/W Description This register will control address engine interrupt for each channel of Bank B. Bit n is for channel n. 0:disable address engine interrupt for channel n 1:enable address engine interrupt for channel n Register E0h E0h (CSO & ALPHA & FMS) (for Bank A & Bank B) Default Value: XXXXXXXXh Access: Read/Write Bit 31:16 15:4 3:0 Access R/W R/W R/W (CSO) begin sample. Description is the offset of current sample relative to loop
(ALPHA) is sample interpolation coefficient, which stands for the linear interpolation ratio between current sample and the next one. (FMS) is Frequency Modulation Step.
Register E4h ( LBA) (for Bank A & Bank B) Default Value: XXXXXXXXh Access: Read/Write Bit 31 30:0 Access R/W R/W Description (CPTR) is reserved for internal use of cache control is the linear address of loop begin sample. It should be word aligned when sample type is 16-bit Mono or 8-bit Stereo; and should be double word aligned when sample type is 16-bit Stereo. Register E8h (ESO & DELTA) (for Bank A & Bank B) 336 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Default Value: XXXXXXXXh Access: Read/Write Bit 31:16 15:0 Access R/W R/W (ESO) sample. Description is the offset of loop end sample relative to loop begin
(DELTA) is sample change step in format 4.12 (Four bits integer, 12 bits fraction), which stands for the frequency ratio: Fs/48KHz, while Fs is the sum of sample rate and pitch shifting rate
Register Ech (Bank A LFO_CTRL & LFO_CT & FMC & RVOL & CVOL) (Bank A Only) Default Value: XXXXXXXXh Access: Read/Write Bit 31:28 27 Access R/W R/W Description (SIN) Sine wave value. (SIN_S) sign bit of sine wave. 0:positive 1:negative (SIN_D) counter direction bit. 0:up 1:down (LFO_R) LFO counter clock rate select bits. 00:48kHz 01:48kHz/4 10:48kHz/16 11:48kHz/64 (LFO_CT)LFO working counter. (FMC) FM modulation control bits. 00:FMA = (FMS * SIN) >> 3 01:FMA = (FMS * SIN) >> 2 10:FMA = (FMS * SIN) >> 1 11:FMA = (FMS * SIN) >> 0 (RVOL)Reverb Send Linear Volume format: 1.6, 7Fh stands for 2x gain, 40h stands for no gain no attenuation, 00h stands for mute. Chorus Send Linear Volume format: 1.6, 7Fh stands for 2x gain, 40h stands for no gain no attenuation, 00h stands for mute.
26
R/W
25:24
R/W
23:16 15:14
R/W R/W
13:7
R/W
6:0
R/W
Preliminary V.10 Oct.07,1999
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Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register ECh (Bank B ATTRIBUTE & FMC & RVOL & CVOL) (Bank B Only) Default Value: XXXXXXXXh Access: Read/Write Bit 31:19 31:30 Access R/W R/W (ATTRIBUTE) Description Channel attribute
PB/REC Select 00:(Normal PB) Normal playback This is a normal playback channel in Bank B with Global Volume, Channel Volume, PAN, SRC, FM/AM features. In this case, bit[29:19] doesn' t matter. 01:(Special PB) Special playback This channel can be one of several kinds of special playback channels. Bit[29:26] is used to select special playback type; bit[25:24] is used to select data flow from channel to FIFO; and bit[23:19] is used to enable/disable individual functions. 10:(REC) Recording to system memory This channel can be one of several kinds of recording channels. Bit[29:26] is used to select recording type; bit[25:24] is used to control how MONO sample is generated when recording; bit[23] is used to enable/disable SRC; bit[22:19] doesn' t matter. 11:(REC_PB) Recording to system memory and playback to mixer This channel is a Recording channel which records sample data to system memory and playback to Main Mixer in the mean time. In this case, bit[29:26] is used to select recording type; bit[25:24] is used to control how MONO sample is generated when recording; and bit[23:19] is used to enable/disable individual functions.
29:26
R/W
Channel Type Select when Bit[31:30] is 00: (Normal PB) xxxx reserverd when Bit[31:30] = 01: (Special PB) 0000 playback to MODEM LINE1 Output FIFO 0001 playback to MODEM LINE2 Output FIFO 0010 playback to PCM L/R Output FIFO 0011 playback to HSET Output FIFO 0100 playback to I2S L/R Output Buffer 0101 playback to CENTER/LFE Output FIFO 338 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0110 playback to SURR L/R Output FIFO 0111 playback to SPDIF L/R Output FIFO other reserved when Bit[31:30] = 1x: (REC or REC_PB) 0000 recording from MODEM LINE1 Input FIFO 0001 recording from MODEM LINE2 Input FIFO 0010 recording from PCM L/R Input FIFO 0011 recording from HSET Input FIFO 0100 recording from I2S L/R Input FIFO 0101 recording from MIC Input FIFO 0110 main mixer capture from PCM L/R Output FIFO 0111 main mixer capture from MMC L/R Output Buffer 1000 Reverb Send 1001 Chorus Send other reserved 25:24 R/W Special Playback Channel to FIFO data flow select / Recording to MONO control When channel is in Special PB mode, this register is used to select input source of a stereo playback slot pairs such as PCM L/R, SURR L/R, CENTER/LFE, I2S L/R and SPDIF L/R. The input source of L/R can be from one channel or can be from two independent channels. When channel is in REC or REC_PB mode, this register is used to control how MONO sample is generated. when Bit[31:30] = 00 (Normal PB) xx never used
when Bit[31:30] = 01 (Special PB) 00 Channel L/R to FIFO L/R Channel Left a FIFO Left Channel Right a FIFO Right 01 Channel L to FIFO L Data flow: Preliminary V.10 Oct.07,1999 339 Silicon Integrated Systems Corporation
In this case, channel is acting as a stereo channel, data flow is like
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Channel Left a FIFO Left 10 Channel R to FIFO R Data flow: Channel Right a FIFO Right 11 reserved when Bit[31:30] = 1x (REC or REC_PB) 00: 01: 10: 11: 23 R/W left, right (left+right+1)/2 reserved.
SRC Enable 0:disable 1:enable FM and AM Enable 0:disbale 1:enable PAN Enable 0:disable 1:enable Channel Volume Enable 0:disable 1:enable Global Volume Enable 0:disable 1:enable Reserved FM modulation control bits. 00:FMA = (FMS * SIN) >> 3 01:FMA = (FMS * SIN) >> 2 10:FMA = (FMS * SIN) >> 1 11:FMA = (FMS * SIN) >> 0 Reverb Send Linear Volume format: 1.6, 7Fh stands for 2x gain, 40h stands for no gain no attenuation, 00h stands for mute. Chorus Send Linear Volume 340 Silicon Integrated Systems Corporation
22
R/W
21
R/W
20
R/W
19
R/W
18:16 15:14
R/W R/W
13:7
R/W
6:0
R/W
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset format: 1.6, 7Fh stands for 2x gain, 40h stands for no gain no attenuation, 00h stands for mute. Register F0h (Bank A GVSEL & PAN & VOL & CTRL & Ec) (for Bank A only) Default Value: XXXXXXXXh Access: Read/Write Bit 31 Access R/W Description (GVSEL) is global volume select bit. 0:select MUSICVOL 1:select WAVEVOL (PAN) is Positioning attenuation control. selects attenuated channel. 0: left, 1: right is the attenuation value in format of 4.2. 3Fh stand for mute. (VOL) is channel volume attenuation in format of 5.3. 00h stands for 0 dB attenuation, FFh stands for mute. are control bits. selects 8/16 bit sample data 0:8-bit data 1:16-bit data selects mono/stereo sample data 0:mono 1:stereo selects unsigned/signed sample data 0:unsigned 1:signed is loop mode enable bit. 0:disable 1:enable is current envelope in format of 6.6 (Six bits integer and six bits fraction). 00h stands for 0dB, FFh stands for -63.984375 dB.
30:24 30 29:24 23:16 15:12 15
R/W R/W R/W R/W R/W R/W
14
R/W
13
R/W
12
R/W
11:0
R/W
Register F0h (Bank B GVSEL & PAN & VOL & CTRL & Bank A LFO_INIT) Default Value: XXXXXXXXh Access: Read/Write Bit 31 Access R/W Description (GVSEL) is global volume select bit. 0:select MUSICVOL 1:select WAVEVOL 341 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 30:24 30 29:24 23:16 R/W R/W R/W R/W (PAN) is Positioning attenuation control.
selects attenuated channel. 0: left, 1: right. is the attenuation value in format of 4.2. 3Fh stand for mute (LFO_INIT) is Bank A per channel LFO counter initial and reload value. Note:Any time when host write to RegECh[26:16] (LFO_CT), LFO_INIT should be written with the same value. are control bits. selects 8/16 bit sample data 0:8-bit data 1:16-bit data selects mono/stereo sample data 0:mono 1:stereo selects unsigned/signed sample data 0:unsigned 1:signed is loop mode enable bit. 0:disable 1:enable (VOL) is channel volume attenuation in format of 6.6. 000h stands for 0 dB attenuation, FFFh stands for mute.
15:12 15
R/W R/W
14
R/W
13
R/W
12
R/W
11:0
R/W
Register F4h (EBUF1) ( Bank A Only) Default Value: XXXXXXXXh Access: Read/Write Bit 31:30 29:28 Access R/W R/W Description (AMS_H) is Amplitude Modulation Step High part. (EMOD) define operation mode. 00:DEC mode ( ramp from 0dB to -64dB ) In this mode, bits 7-0 of this register are used as ECNT which stores current state of a 8-bit counter; bits 15-8 of this register are used as EINIT which provides initial value of that 8-bit counter; bits 27-16 of this register are used as EAMT which is the absolute ramping amount with range from 0dB to 63 and 63/64 dB. Every 48KHz clock, ECNT decrease 1; every time when ECNT=00h, it reload EINIT, EAMT decrease 1, and Ec Preliminary V.10 Oct.07,1999 342 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset decrease 1; every time when EAMT=00h, envelope engine will toggle buffer flag in global register CEBC. 01:INC mode ( ramp from -64dB to 0dB ) In this mode, the layout of this register is completely the same as in DEC mode. Engine works in the same way except that the ramp direction is from -64dB to 0dB. 10:Delay mode In this mode, bits 27-26 are used to select sub-mode: 00:Delay_hold 01:Delay_start 10:Delay_stop 11:reserved 19-0 is used as EDLY which store the current state of a 20-bit delay counter, bits 25-20 are of no use. Every 48 KHZ clock, EDLY decrease 1. During all the time this buffer active, Ec keep unchanged. In Delay_hold sub-mode, when EDLY =00000h, engine will toggle current buffer flag in global register CEBC. In Delay_start sub-mode, when EDLY =00000h, engine will reset DLY flag register. In Delay_stop sub-mode, when EDLY =00000h, engine will reset start/stop flag register. 11:Still mode In this mode, Ec keep unchanged, buffer never toggle automatically. Only when CEBC is written, buffer may toggle. Register F8h (EBUF2) (Bank A Only) Default Value: XXXXXXXXh Access: Read/Write Bit 31:0 Access R/W Description EBUF2 is totally as the same as EBUF1except that bits 31-30 are AMS_L (Amplitude Modulation Step Low part).
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15
15.1
Register Summary / Description - SMBus
SMBUS Control Registers
Byte Length 1 1 1 1 1 1 1 1 8 1 1 1 1 Access R/WC R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W SMBUS Status SMBUS Enable SMBUS Control SMBUS Host Control SMBUS Address SMBUS Command SMBUS Processed Byte Count SMBUS Byte Count SMBUS Byte0~7 SMBUS Device Address SMBUS Device Byte 0 SMBUS Device Byte 1 SMBUS Host Slave Alias Address Name Abbreviate SMB_STS SMB_EN SMB_CNT SMBHOST_CNT SMB_ADDR SMB_CMD SMB_PCOUNT SMB_COUNT SMB_BYTE0~7 SMBDEV_ADDR SMB_DB0 SMB_DB1 SMB_SAA
Offset 80 81 82 83 84 85 86 87 88 90 91 92 93
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16 16.1
Register Summary / Description - ACPI Summary
ACPI Configuration Registers
Byte Length 2 2 2 2 4 4 4 1 1 4 2 2 2 2 2 4 2 2 2 2 2 2 4 2 2 2 2 2 2 2 Access R/WC R/W R/W RO RO RO R/W RO RO RO R/W WO RO R/WC R/W R/W R/W R/W WO RO R/WC R/W R/W R/W R/W R/W R/W R/WC R/W R/W Name Power Management Status Power Management Enable Power Management Control Reserved Power Management Timer Reserved Processor Control Processor Power State Level 2 Processor Power State Level 3 Reserved Fix Feature Control PM1_STS Write Port Reserved General Purpose Event 0 Status General Purpose Event 0 Enable GPE0 Interrupt Routing GPE0 Trigger Mode Select General Purpose Event Control GPE0_STS Write Port Reserved General Purpose Event 1 Status General Purpose Event 1 Enable GPE1 Interrupt Routing GPE1 Trigger Mode Select GPE1 Pin Level GPE1 I/O Mode Select GPE1 Input Polarity Select Legacy Event Status Legacy Event Enable Device Activity Status 345 GPE1_STS GPE1_EN GPE1_ROUT GPE1_TRG GPE1_LVL GPE1_IO GPE1_POL LEG_STS LEG_EN DEVACT_STS GPE0_STS GPE0_EN GPE0_ROUT GPE0_TRG GPE_CNT GPE0_PORT FIX_CNT PM1_PORT P_CNT P_LVL2 P_LVL3 PM_TMR Abbreviate PM1_STS PM1_EN PM1_CNT
Offset 00 02 04 06 08 0C 10 14 15 16 1A 1C 1E 20 22 24 28 2A 2C 2E 30 32 34 38 3A 3C 3E 40 42 44
Preliminary V.10 Oct.07,1999
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 46 48 49 4A 4B 4C 50 52 54 55 56 58 5A 5C 5E 5F 60 62 2 1 1 1 1 4 2 2 1 1 2 2 2 2 1 1 2 2 RO R/W R/W R/W R/W RO R/W R/W R/W R/W R/W WO R/W RO RO R/W RO R/W Reserved SMI# Command Port Mail Box SFTMR Initial Value Software Watchdog Timer Control High Resolution Timer Value PIO Port Trap 0 Address PIO Port Trap 1 Address PIO Port Trap 0 Mask PIO Port Trap 1 Mask Legacy Event Control LEG_STS Write Port IRQ/NMI Wake Control I/O Address Track for SMI# I/O C/BE# Track for SMI I2C Bus Control System Wakeup From S5 Status System Wakeup From S5 Control MUX Function SMICMD_PORT MAIL_BOX SF_TMR SFTMR_CNT HR_TMR IOTRAP0_PORT IOTRAP1_PORT IOTRAP0_MASK IOTRAP1_MASK LEG_CNT LEG_PORT IOQWAK_CNT ADDR_TRACK CBE_TRACK I2C_CNT S5WAK_STS S5WAK_CNT MUX Func. Selection
Pin Name
Default
Input GPIO0 GPI0 PCIREQ3# OC0# GPI1 OC1# GPI2/INST_OFF# LDRQ1# OC3# GPI3 EEDO GPI4 346
Output GPO0 GPI0 APC3B4 APC3B5 APC3B4 APC3B5 APC3B6 APC3B7 APC2B0 APC3B0 APC3B1 APC2B1
GPIO1 GPIO2
GPO1 PCIGNT3# GPO2
GPI1 GPI2
GPIO3
GPO3
GPI3
GPIO4 Preliminary V.10 Oct.07,1999
GPO4
GPI4
Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset APC3B0 APC3B1 GPIO5 GPI5 GPO5 AUXGPO5 GPO6 AUXGPO6 GPO7 S/PDIF GPO8 AUXGPO8 PLED0# GPO10 GPO11 GPO12 GPO13 GPO14 GPO15 GPI5 APC2B1 APC3B0 APC3B1 APC2B1 APC3B0 APC3B1 APC2B2 APC3B0 APC3B1 APC2B3 APC2B4 APC2B5 APC2B6 APC2B5 APC2B6 APC2B5 APC2B6 APC2B5 APC2B6 APC2B5 APC2B6 APC2B7 APC3B0 APC3B1
GPIO6
GPI6
GPI6
GPIO7
GPI7
GPI7
GPIO8
GPI8 OC2# GPI10 KB DAT GPI11 KB CLK GPI12 PS/2 MOUSE DAT GPI13 PS/2 MOUSE CLK GPI14 KB LOCK# GPI15 SMBALT# I2CALT#
GPI8
GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15
GPI10 GPI11 GPI12 GPI13 GPI14 GPI15
1. All IO buffers for GPIOx are in the auxiliary power plane, except for GPIO0, GPIO1, GPIO2, and GPIO7. All GPIOx are general bidirection I/O buffers. The decision on pull-up register or pull-down register depends on the usage of the GPIOx pin. The detail description could be found in the section " PIN DESCRIPTION" .
Preliminary V.10 Oct.07,1999
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16.2
GPIOx Logic
SIS630 supports a variety of General-Purpose Input/Output pins that are also MUXed with other signals as they are shown above with a couple of properties. When they are used as GPIx or GPOx, they can only valid in main power plane. All GPIx can be used as wake-up events or trigger off power management interrupts (SCI#, SMI#, IRQ). The following table and block diagram give a brief of description.
GPIx
GPE1_POL(ACPI 3E~3F)
Triggle Mode Selection
(low/high active level/edge triggle) GPE1_STSx GPE1 WAKE EVENT (wake up from S1,S2)
GPE1_TRG(ACPI 38,39h)
GPE1_EN(ACPI 32,33h) SMI_EN(ACPI42h.0) SMI#
GPE1 WAKE EVENT (wake up from S1,S2) GPE1_ROUT(ACPI 34,35h)
Power Management Interrupt Selection
SCI#
GPEIRQ
Figure 16.2-1 GPIOx Logic
16.3
ACPI Register
The following registers located at I/O base address + the indicated offset value Preliminary V.10 Oct.07,1999 348 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset . The base address is programmed in the Register PCI Configuration space. Register 00h~01h Power Management Status Register (PM1_STS) Default Value: 0000h Access: Read/Write Clear The following registers are all sticky bits and only can be cleared by writing a one to their corresponding fields. Bit 15 Access R/WC Description Wake up Status (WAK_STS) This bit is set when the system is in the sleeping state (S1/S2) and an enabled wake-up event occurs. Upon setting this bit, the system will translate form sleep state to S0 state. Reserved Ignored (Power Button Override Status) RTC Status (RTC_STS) This bit is set when the RTC generates an IRQ8# in S0/S1/S2. While both RTC_EN bit and RTC_STS bit are set, a power management event is raised. Reserved Power Button Status (PWRBTN_STS) This bit is set when the power button is pressed (the PWRBTN# signal is asserted Low). If PWRBTN_STS and PWRBTN_EN are both set under S0 state, then a SCI or SMI# is raised. If PWRBTN_STS bit is set under sleeping state (S1/S2), a WAKE event will be generated. Reserved Global Status (GBL_STS) When the ACPI software attemps to gain the ownership of the Global Lock, this bit would be set by the access to the BIOS_RLS. Bus Master Status (BM_STS) This is the bus master status bit. This bit is set when a system bus master is requesting the system bus. Reserved Power Management Timer Status (PMTMR_STS) This bit will be set if the MSB of PM_TMR is changed from '1' to '0' or '0' to '1'. While PMTMR_STS and PMTMR_EN bit are set, a power management event (SCI or SMI#) is raised.
14:12 11 10
RO R/WC R/WC
9 8
RO R/WC
7:6 5
RO R/WC
4
R/WC
3:1 0
RO R/WC
Register 02h~03h
Power Management Enable Register (PM1_EN) 349 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Default Value: 0000h Access: Read/Write Bit 15:11 10 Access RO R/W Description Reserved RTC Enable (RTC_EN) This bit is used to enable the assertion of the RTC_STS to generate a power management event (Wake and SCI/SMI#). Reserved Power Button Enable (PWRBTN_EN) This bit is used to enable the assertion of the PWRBTN_STS bit to generate a power management event (SCI/SMI#). The system always can wake up from Sx by Power Button regardless of the value of this bit. Reserved Global Enable (GBL_EN) When the BIOS drive releases the lock, this bit is used to enable the assertion of the GBL_STS to generate a SCI. Reserved Power Management Timer Status (PMTMR_EN) This is PMTMR enable bit. If this bit and PMTMR_STS bit are set, then a power management event is generated (SCI/SMI#).
9 8
RO R/W
7:6 5
RO R/W
4:1 0
RO R/W
Register 04h~05h Power Management Control Register (PM1_CNT) Default Value: 0000h Access: Read/Write Bit 15:14 13 Access RO WO Description Reserved Sleep Enable (SLP_EN) This is a wirte only bit and always returns a zero when read. Setting this bit to one will cause the system to enter the sleep state defined by the SLP_TYP field.
Preliminary V.10 Oct.07,1999
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Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 12:10 R/W Sleeping Type (SLP_TYP) Define the power-saving mode that the system should enter when the SLP_EN bit is set to one. 000 : S0 state (Working) 001 : S1 state (STPCLK#) 010 : S2 state (STPCLK# and/or CPUSLP#) 011 : S3 state (Suspend To RAM) 100 : S4 state (Suspend To Disk) 101 : S5 state (Soft_Off) 9:3 2 RO WO Reserved Global Release (GBL_RLS) This bit is used by the ACPI software to raise a SMI# to the BIOS software. Writing a one to this register will generate a BIOS event to set BIOS_STS in LEG_STS. Bus Master Reload Enable (BM_RLD) If enabled, a bus master request will cause any processor in the C3 state to transition to the C0 state. 0 : Disable 1 : Enable 0 R/W SCI Enable (SCI_EN) Selects the power management event in PM1 to be either SCI or SMI#. When this bit is set, a power management event will generate SCI. When this bit is reset, a power management event will generate SMI#. Reversed
1
R/W
Register 06h~07h
Register 08h~0Bh ACPI Power Management Timer Register (PM_TMR) Default Value: Free Running Access: Read Only Bit 31:24 23:0 Access RO RO Reserved Power Management Timer Value This read-only field reflects the current counting of the power management timer. The PM_TMR value will be reset when the system enter one of the sleeping state (S1~S5). Reading to this field will stop the running of PM_TMR. Reversed 351 Silicon Integrated Systems Corporation Description
Register 0Ch~0Fh
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 10h~13h ACPI Processor Control Register (P_CNT) Default Value: 0000 0000 Access: Read/Write Bit 31:5 4 3:1 Access RO R/W R/W Reserved Throttling Function Enable This bit enables the C0 clock throttling function. Throttling Duty Cycle Control This 3-bit field determines the duty cycle of the STPCLK# signal when the system is in the C0 throttling mode. Bits 000 001 010 011 100 101 110 111 0 RO Reserved Performance Rate 100% 12.5% 25% 37.5% 50% 62.5% 75% 87.5% Description
Register 14h ACPI Processor Power State Level 2 (P_LVL2) Default Value: 00 Access: Read Only Bit 7:0 Access RO Description Enter C2 Power State Register Reading to this register returns all zeros; writes to this register have no effect. Reads to this register will also generate a " Enter C2 power state " event.
Register 15h ACPI Processor Power State Level 3 (P_LVL3) Default Value: 00 Access: Read Only Bit 7:0 Access RO Description Enter C3 Power State Register Reading to this register returns all zeros; writes to this register have no effect. Reads to this register will also generate a " Enter C3 power state " event. 352 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 16h~19h Reversed
Register 1Ah~1Bh ACPI Fix Feature Control Register (FIX_CNT) Default Value: 0040 Access: Read Only Bit 15:10 9 Access RO R/W Reserved PM Timer Test Mode Enable 0 : Disable 1 : Enable ACPI Fix Feature Test Mode Enable 0 : Disable 1 : Enable PM1_STS Write Port Enable (PM1PORT_EN) If this bit is enabled, writing a one to PM1_PORT register will cause the corresponding bit in PM1_STS to be set. 0 : Disable 1 : Enable Power Button Override Function Enable When this bit is reset, the power button override function will be disabled. 0 : Disable 1 : Enable 5:4 R/W Power Button Trigger Mode Selection The value in this field can select the trigger mode of power button. If the level mode is selected, PWRBTN_STS will always be set during the period of pressing power button. If the edge mode is selected, PWRBTN_STS can only be set once according to the power button is pressed or released. 00 : Level Mode 01 : Button press edge mode 10 : Button release edge mode 11 : Reversed 3 R/W CPUSLP# Enable If this bit is set, CPUSLP# can be asserted for PII system to enter deep sleep state under S2. 0 : Disable 1 : Enable Preliminary V.10 Oct.07,1999 353 Silicon Integrated Systems Corporation Description
8
R/W
7
R/W
6
R/W
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 2 1 0 RO WO RO Reserved BIOS Release (BIOS_RLS) The ACPI software can set GBL_STS by writing a one to this field. Reserved
Register 1Ch~1Dh PM1_STS Write Port (PM1_PORT) Default Value: 0000 Access: Write Only Bit 15:0 Access WO Description PM1_STS Write Port Writing a one to this register will cause the corresponding field of PM1_STS to be set. Before writing to this register, PM1PORT_EN must be set. Reversed
Register 1Eh~1Fh
Register 20h~21h General Purpose Event 0 Status Register (GPE0_STS) Default Value: 0000h Access: Read/Write Clear The following registers are all sticky bits and only can be cleared by writing a one to their corresponding fields. When one of status and their corresponding enable bits are set in S1/S2, a wakeup event is generated. If the status and the corresponding rerouting bits are set during working state (S0), an SCI/SMI#/IRQ will be generated. Note that IRQWAK_STS, USBWAK_STS, and EXTSMIWAK_STS can only be set during sleeping state. Bit 15 Access R/WC Description IRQ Wake Status (IRQWAK_STS) This bit is set when one of the enabled 8259 IRQ wakeup events is generated in S1/S2 state. Note: The IRQ wake-up events are defined in IRQWAK_CNT register. 14 R/WC USB Wake Status (USB3_STS) This bit is set when ACPI circuit detects a wake up event in sleeping state (S1/S2). The wake-up event is occurred from USB port0,1,2. Reserved MAC Power Management Event Status (MACPME_STS) This bit is set when internal MAC power management event is generated. 354 Silicon Integrated Systems Corporation
13 12
RO R/WC
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 11 R/WC PCI Power Management Event Status (PCIPME_STS) This bit is set when PCI power management event is asserted for more than 4ms. BS-Audio Power Management Event Status (BSAUDPME_STS) This bit is set when an internal Baseline Audio power management event is generated. Keyboard Controller Status (KBC_STS) This bit is set when an internal keyboard controller hotkey event (CTRL+ALT+Backspace) is generated. Ring Indication Status (RING_STS) This bit is set when the RING goes active for more than 4ms. This bit can be choosed as quite or noise mode in GPECNT register. In quite mode, RING_STS can only be set during sleeping state (S1/S2). In noisy mode, RING_STS can be set in working and sleeping states. SMBus Interrupt/I2C Alert Status (SMBINT_STS/I2CALT_STS) If SMBus mode is selected, this bit will be set when a SMB interrupt is generated. If I2C mode is selected, this bit will be set when I2CALT# goes active. Reserved Audio Controller Power Management Event Status (AUDPME_STS) This bit is set when an internal AC' 97 power management event is generated. USB Wake Status (USBWAK2_STS) This bit is set when internal USB host controller detects a wake up event in sleeping state (S1/S2). The wake-up event is occurred from USB port3,4. EXTSMI# Wake Status (EXTSMIWAK_STS) This bit is set when EXTSMI# goes active in sleeping state (S1/S2). EXTSMI# Status (EXTSMI_STS) This bit is set when EXTSMI# goes active in working state (S0). Thermal Event Override Status (THRMOR_STS) This bit is set when THERM# goes active for more than 2 seconds. If THRMOR_DTY and THRMOR_THT are set, the system will enter thermal throttling mode. 355 Silicon Integrated Systems Corporation
10
R/WC
9
R/WC
8
R/WC
7
R/WC
6 5
RO R/WC
4
R/WC
3
R/WC
2 1
R/WC R/WC
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0 R/WC Thermal Event Status (THRM_STS) This bit is set when THERM# goes active.
Register 22h~23h General Purpose Event 0 Enable Register (GPE0_EN) Default Value: 0000h Access: Read/Write Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Access R/W R/W RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W Description IRQ Wake Enable (IRQWAK_EN) USB Wake Enable (USB3WAK_EN) Reserved MAC Power Management Event Enable (MACPME_EN) PCI Power Management Event Enable (PCIPME_EN) BS-Audio Controller (BSAUDPME_EN) PowerManagement Event Enable
Keyboard Controller Enable (KBC_EN) Ring Indication Enable (RING_EN) SMBus Interrupt/I2C Alert Enable (SMBINT_EN/I2CALT_EN) Reserved Audio Controller (AUDPME_EN) Power Management Event Enable
USB Wake Enable (USB2WAK_EN) EXTSMI# Wake Enable (EXTSMIWAK_EN) EXTSMI# Enable (EXTSMI_EN) Thermal Event Override Enable (THRMOR_EN) Thermal Event Enable (THRM_EN)
Register 24h~27h General Purpose Event 0 Interrupt Routing Register (GPE0_ROUT) Default Value: 0000 0000h Access: Read/Write The following registers are GPE0 routing registers. If one of GPE0_STS is set and its corresponding GPE0_ROUT register is routing to SCI/SMI#/GPEIRQ, an SCI/SMI#/GPEIRQ will be generated. Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 31:30 R/W IRQ Wake Route (IRQWAK_ROUT) 00 : No effect 01 : SMI# 10 : SCI 11 : GPEIRQ USB Wake Route (USBWAK3_ROUT) Reserved MAC Power Management Event Route (MACPME_ROUT) PCI Power Management Event Route (PCIPME_ROUT) BS-Audio Controller Power Management Event Route (BSAUDPME_ROUT) 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 R/W R/W R/W RO R/W R/W R/W R/W R/W R/W Keyboard Controller Route (KBC_ROUT) Ring Indication Route (RING_ROUT) SMBus/I2C Route (SMBINT_ROUT/I2CALT_ROUT) Reserved Audio Controller (AUDPME_ROUT) Power Management Event Route
29:28 27:26 25:24 23:22 21:20
R/W RO R/W R/W RO
USB Wake Route (USB2WAK_ROUT) EXTSMI# Wake Route (EXTSMIWAK_ROUT) EXTSMI# Route (EXTSMI_ROUT) Thermal Event Override Route (THRMOR_ROUT) Thermal Event Route (THRM_ROUT)
Register 28h~29h General Purpose Event 0 Trigger Mode Selection (GPE0_TRG) Default Value: 0000h Access: Read/Write If GPE0 is set to level trigger mode, the GPE0_STS will always be set by the active event as long as the event is not de-asserted. If GPE0_TRG is set to be edge trigger mode, the active event can only set GPE0_STS once before the active event is de-asserted. Bit 15 Access R/W Description IRQ Wake Trigger (IRQWAK_TRG) 0 : Level trigger mode 1 : Edge trigger mode USB Wake Trigger (USB3WAK_TRG) 357 Silicon Integrated Systems Corporation
14
R/W
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RO R/W R/W R/W R/W R/W R/W RO R/W R/W R/W R/W R/W R/W Reserved MAC Power Management Event Trigger (MACPME_TRG) PCI Power Management Event Trigger (PCIPME_TRG) BS-Audio Power Management Event Trigger (BSAUDPME_TRG) Keyboard Controller Trigger (KBC_TRG) Ring Indication Trigger (RING_TRG) SMBus/I2C Trigger (SMBINT_TRG/I2CALT_TRG) Reserved Audio Controller (AUDPME_TRG) Power Management Event Trigger
USB Wake Trigger (USB2WAK_TRG) EXTSMI# Wake Trigger (EXTSMIWAK_TRG) EXTSMI# Trigger (EXTSMI_TRG) Thermal Event Override Trigger (THRMOR_TRG) Thermal Event Trigger (THRM_TRG)
Register 2Ah~2Bh General Purpose Event Control (GPE_CNT) Default Value: 0000h Access: Read/Write Bit 15:8 7 Access RO R/W Reserved GPE0_STS Write Port Enable (GPE0PORT_EN) If this bit is enabled, writing a one to GPE0_PORT register will cause the corresponding bit in GPE0_STS to be set. 0 : Disable 1 : Enable RING Indication Quite/Noisy Mode Control (RING_CNT) If RING is set to be quite mode, RING_STS can only be set in sleeping state (S1/S2). If the noisy mode is selected, RING_STS can be set in working and sleeping state. 0 : Noisy mode 1 : Quite mode Description
6
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5 R/W SMBus/I2C Function Select (SMB_SEL) If this bit is set to one, SMBDAT/I2CDAT, SMBCLK/I2CCLK, and SMBALT#/I2CALT# will be switched as I2C mode. Otherwise, they will be selected as SMBus mode. 0 : SMBus mode select 1 : I2C mode select 4 3 RO R/W Reserved Thermal Override Throttling Function Enable (THRMOR_THT) This bit enables the thermal override throttling function. 0 : Disable 1 : Enable 2:0 R/W Thermal Override Throttling Duty Cycle Control This 3-bit field determines the duty cycle of the STPCLK# signal when the thermal override event is generated. Bits 000 001 010 011 100 101 110 111 Performance Rate 100% 12.5% 25% 37.5% 50% 62.5% 75% 87.5%
Register 2Ch~2Dh GPE0_STS Write Port (GPE0_PORT) Default Value: 0000 Access: Write Only Bit 15:0 Access WO Description GPE0_STS Write Port Writing a one to this register will cause the corresponding field of GPE0_STS to be set. Before writing to this register, GPE0PORT_EN must be set.
Register 2Eh~2Fh
Reversed
Register 30h~31h General Purpose Event 1 Status Register (GPE1_STS) Default Value: 0000h Access: Read/Write Clear Preliminary V.10 Oct.07,1999 359 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset The following registers are all sticky bits and only can be cleared by writing a one to their corresponding fields. When one of status and their corresponding enable bits are set in S1/S2, a wakeup event is generated. If the status and the corresponding rerouting bits are set during working state (S0), an SCI/SMI#/IRQ will be generated. Not that if GPIO[n] are selected as output mode or their mux-ed function, their corresponding status bits must be ignored. So do their enable and route registers must be set to zero. Bit 15:3 2 Access R/WC R/WC Description GPIO[15:0] Status (GPIO[15:3]_STS) This bit is set when one of GPIO[15:0] event goes active. GPIO2 Status/ Instant Power-off Status (GPIO2_STS/INSTOFF_STS) This bit is set when GPIO2 event goes active. If LPC bridge configuration register 48h[05] is enabled, the assertion of GPIO2_STS would power off the machine compulsively. GPIO[1:0] Status (GPIO[1:0]_STS) This bit is set when one of GPIO[1:0] event goes active.
1:0
R/WC
Register 32h~33h General Purpose Event 1 Enable Register (GPE1_EN) Default Value: 0000h Access: Read/Write Bit 15:0 Access R/W Description GPIO[15:0] Enable (GPIO[15:0]_EN)
Register 34h~37h General Purpose Event 1 Interrupt Routing Register (GPE1_ROUT) Default Value: 0000 0000h Access: Read/Write The following registers are GPE1 routing registers. If one of GPE1_STS is set and its corresponding GPE1_ROUT register is routing to SCI/SMI#/GPEIRQ, an SCI/SMI#/GPEIRQ will be generated. Bit 31:30 Access R/W Description GPIO15 Route (GPIO15_ROUT) 00 : No effect 01 : SMI# 10 : SCI 11 : GPEIRQ GPIO[14:0] Route (GPIO[14:0]_ROUT) See ths pattern of GPIO15_ROUT. General Purpose Event 1 Trigger Mode Selection (GPE1_TRG) 360 Silicon Integrated Systems Corporation
29:0
R/W
Register 38h~39h
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Default Value: 0000h Access: Read/Write If GPE1 is set to level trigger mode, the GPE1_STS will always be set by the active event as long as the event is not de-asserted. If GPE1_TRG is set to be edge trigger mode, the active event can only set GPE1_STS once before the active event is de-asserted. Bit 15:0 Access R/W Description GPIO[15:0] Trigger (GPIO[15:0]_TRG) 0 : Level trigger mode 1 : Edge trigger mode
Register 3Ah~3Bh General Purpose Event 1 Pin Level (GPE1_LVL) Default Value: 0000h Access: Read/Write If GPIO[n] is set to input mode, the input level of its corresponding GPIO pin can be read from this register. If GPIO[n] is set to output mode, the output level can be control through this register. Note that the output value of GPIO[n] must be written to this register before GPIO[n] is switch to output mode. Bit 15:0 Access R/W Description GPIO[15:0] Pin Level (GPIO[15:0]_LVL) 0 : Pin input level low/Pin output level low 1 : Pin input level high/Pin output level high
Register 3Ch~3Dh General Purpose Event 1 Input/Output Mode Select (GPE1_IO) Default Value: FFFFh Access: Read/Write Bit 15:0 Access R/W Description GPIO[15:0] Input/Output Mode Select (GPIO[15:0]_IO) 0 : Output Mode 1 : Input Mode
Register 3Eh~3Fh General Purpose Event 1 Input Polarity Select (GPE1_POL) Default Value: 0000h Access: Read/Write Bit 15:0 Access R/W Description GPIO[15:0] Input Polarity Select (GPIO[15:0]_POL) 0 : Active low 1 : Active high Legacy Event Status Register (LEG_STS) 361 Silicon Integrated Systems Corporation
Register 40h~41h
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Default Value: 0000h Access: Read/Write Clear The following registers are all sticky bits and only can be cleared by writing a one to their corresponding fields. Bit 15 Access R/WC Description Software Watch Dog Timer Event 1 Status (SFTMR1_STS) This bit is set when the software watchdog timer expires the second time. This status bit does not have its corresponding enable bit and can survive under PCIRST#. Software Watch Dog Timer Event 0 Status (SFTMR1_STS) This bit is set when the software watchdog timer expires the first time. This status bit does not have its corresponding enable bit and can survive under PCIRST#. General Purpose Event Status (GPESMI_STS) This bit is set when the SMI# is caused by GPE0 or GPE1. This status bit does not have its corresponding enable bit. Power Management Status (PM1SMI_STS) This bit is set when the SMI# is caused by PM1. This status bit does not have its corresponding enable bit. Legacy USB Status (LEGUSB_STS) This bit is set when a legacy USB SMI# is activated and only used for port 0,1,2. Legacy USB Status (LEGUSB_STS) This bit is set when a legacy USB SMI# is activated and only used for port 3,4. Serial IRQ SMI# Status (SIRQSMI_STS) This bit is set when internal Serial IRQ decoder asserts an SMI#. LPC SMI# Status (LPCSMI_STS) This bit is set when internal LPC controller asserts an SMI#. One Minute Status (ONEMIN_STS) This bit is set every one minute. In legacy power management, ONEMIN_STS and ONEMIN_EN can be used to monitor the device status every one minute. RTC Year 2000 Roll Over Status (RTCY2K_STS) This bit is set when the 9th bit of RTC time register rolls from 99 to 00. This bit can be used to monitor the Y2K event.
14
R/WC
13
R/WC
12
R/WC
11
R/WC
10
R/WC
9 8 7
R/WC R/WC R/WC
6
R/WC
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5 4 R/WC R/WC SMI# Command Status (SMICMD_STS) This bit is set when OS write a value to SMI# command port. BIOS Status (BIOS_STS) This bit is set when the BIOS driver write a one to GBL_RLS in PM1_CNT register. Input/Output Trap 1 Status (IOTRAP1_STS) This bit is set when software initiates an I/O access to the range of IOTRAP1_PORT and IOTRAP1_MASK Input/Output Trap 0 Status (IOTRAP0_STS) This bit is set when software initiates an I/O access to the range of IOTRAP0_PORT and IOTRAP0_MASK Reserved SMI# Status (SMI_STS) This bit is set when one of the SMI# source is activated. The SMI# will be masked for 128 PCI clock after clearing this bit.
3
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2
R/WC
1 0
RO R/WC
Register 42h~43h Legacy Event Enable Register (LEG_EN) Default Value: 0000h Access: Read/Write Bit 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Access RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W Reserved USB PORT 0,1,2 SMI# Enable USB Port 3,4 SMI# Serial IRQ SMI# Enable (SIRQSMI_EN) LPC SMI# Enable (LPCSMI_EN) One Minute Enable (ONEMIN_EN) RTC Year 2000 Roll Over Enable (RTCY2K_EN) SMI Command Enable (SMICMD_EN) BIOS Enable (BIOS_EN) Input/Output Trap 1 Enable (IOTRAP1_EN) Input/Output Trap 0 Enable (IOTRAP0_EN) Reserved SMI Enable (SMI_EN) 363 Silicon Integrated Systems Corporation Description
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 44h~45h Device Activity Status Register (DEVACT_STS) Default Value: 0000h Access: Read/Write Clear The following registers are all sticky bits and only can be cleared by writing a one to their corresponding fields. Bit 15 Access R/WC Description Primary IDE Activity Status (IDEPACT_STS) This bit is set when software initiates an I/O access to the range of 170h~177h and 376h. Secondary IDE Activity Status (IDESACT_STS) This bit is set when software initiates an I/O access to the range of 1F0h~1F7h and 3F6h. Reserved Sound Blaster Activity Status (SBACT_STS) This bit is set when software initiates an I/O access to the range of 220h~233h, 240h~253h, 260h~273h, and 280h~293h. Microsoft Sound Activity Status (MSSACT_STS) This bit is set when software initiates an I/O access to the range of 530h~537h, 604h~60Bh, E80h~E87h, and F40h~F47h. MIDI Activity Status (MIDIACT_STS) This bit is set when software initiates an I/O access to the range of 300h~303h, 310h~313h, 320h~323h, and 330h~333h. Keyboard Controller Activity Status (KBCACT_STS) This bit is set when software initiates an I/O access to the range of 60h and 64h. Game Port Activity Status (GAMEACT_STS) This bit is set when software initiates an I/O access to the range of 200h~207h and 388h~38Bh. Floopy Activity Status (FLPYACT_STS) This bit is set when software initiates an I/O access to the range of 3F0h~3F7h and 370h~377h. Serial Port Activity Status (SERACT_STS) This bit is set when software initiates an I/O access to the range of 2E8h~2EFh, 2F8h~2FFh, 3E8h~3EFh, and 3F8h~3FFh. Parallel Port Activity Status (PARLACT_STS) This bit is set when software initiates an I/O access to the range of 278h~27Fh, 378h~37Fh, and 3BCh~3BEh. 364 Silicon Integrated Systems Corporation
14
R/WC
13:12 11
RO R/WC
10
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9
R/WC
8
R/WC
7
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6
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5
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4
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Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3 2 1 0 R/WC R/WC R/WC R/WC INTD# Activity Status (INTDACT_STS) This bit is set when PCI INTD# goes active. INTC# Activity Status (INTCACT_STS) This bit is set when PCI INTC# goes active. INTB# Activity Status (INTBACT_STS) This bit is set when PCI INTB# goes active. INTA# Activity Status (INTAACT_STS) This bit is set when PCI INTA# goes active.
Register 46h~47h
Reversed
Register 48h SMI# Command Port Register (SMICMD_PORT) Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description SMI# Command Port Value Writing to this register will generate an SMI# command event.
Register 49h Mail Box Register (MAIL_BOX) Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Read/Write Free Byte Description
Register 4Ah Software Watchdog Timer Initial Value (SF_TMR) Default Value: FFh Access: Read/Write Bit 7:0 Access R/W Description Software Watchdog Timer Initial Value Writing to this register will reload the software watchdog timer with the value specified in this register. If the software watchdog timer expires the first time, the expired event will set the SFTMR0_STS and the timer will reload its initial value and count again. If the timer expire the second time, the expired event will set the SFTMR1_STS. The timer value can' t be read from this field.
Register 4Bh Software Watchdog Timer Control Register (SFTMR_CNT) Default Value: 00h Preliminary V.10 Oct.07,1999 365 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Access: Bit 7 Read/Write Access R/W Description Software Watchdog Timer Counting Enable The software watchdog timer will start to count when this bit is set to one. Reserved Software Watchdog Timer Clock Select 00 : 4ms 01 : 1sec 10 : 1min 11 : 1hour Software Watchdog Timer Expiration Event 1 Routing Select When SFTMR1_STS is set to one, an SMI#/SFTIRQ/PCIRST# will be generated according to the following combination. 00 : No effect 01 : SMI# 10 : SFTIRQ 11 : PCIRST# 1:0 R/W Software Watchdog Timer Expiration Event 0 Routing Select When SFTMR0_STS is set to one, an SMI#/SFTIRQ/PCIRST# will be generated according to the following combination. 00 : No effect 01 : SMI# 10 : SFTIRQ 11 : PCIRST#
6 5:4
RO R/W
3:2
R/W
Register 4Ch~4Fh High Resolution Timer Counting Value (HR_TMR) Default Value: 0000 0000h Access: Read Only Bit 31:0 Access RO Description High Resolution Timer Value This read-only field reflects the current counting of HR_TMR. The clock source can be applied from MAC or AC' 97. If this tmer is disabled, the counting value will be reset to zero. Note: The control register of PM_TMR is located in LEG_CNT.
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 50h~51h Programmable 16-bits I/O Port Trap 0 Address (IOTRAP0_PORT) Default Value: 0000h Access: Read/Write Bit 15:0 Access R/W Description I/O Port Trap 0 Address Any I/O access to the range of IOTRAP0_PORT and IOTRAP0_MASK will cause IOTRAP0_STS to be set to one.
Register 52h~53h Programmable 16-bits I/O Port Trap 1 Address (IOTRAP1_PORT) Default Value: 0000h Access: Read/Write Bit 15:0 Access R/W Description I/O Port Trap 1 Address Any I/O access to the range of IOTRAP1_PORT and IOTRAP1_MASK will cause IOTRAP1_STS to be set to one.
Register 54h Programmable 16-bits I/O Port Trap 0 Mask (IOTRAP0_MASK) Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description I/O Port Trap 0 Mask A one in this register will select the low 8-bit mask for IOTRAP0_PORT.
Register 55h Programmable 16-bits I/O Port Trap 1 Mask (IOTRAP1_MASK) Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description I/O Port Trap 0 Mask A one in this register will select the low 8-bit mask for IOTRAP1_PORT.
Register 56h~57h Legacy Event Control (LEG_CNT) Default Value: 0000h Access: Read/Write Bit 15:8 Access RO Description Reserved
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7 R/W LEG_STS Write Port Enable (LEGPORT_EN) If this bit is enabled, writing a one to LEG_PORT register will cause the corresponding bit in LEG_STS to be set. 0 : Disable 1 : Enable 6:4 3:2 RO R/W Reserved High Resolution Timer Clock Source Select 00 : MAC 25MHz/25 (1MHz) 01 : Reserved 10 : AC' 97 12.288MHz/12 (1024KHz) 11 : AC' 97 12.288MHz/16 (768KHz) High Resolution Timer Counting Enable If HR_TMR is disabled, the HR_TMR value will be reset to zero. 0 : Disable 1 : Enable 0 R/W SMI# Mask Interval Select If SMI_STS is cleared, the SMI# will be masked a certain time according to this register. 0 : 128 PCICLK 1 : 8 PCICLK Register 58h~59h LEG_STS Write Port (LEG_PORT) Default Value: 0000h Access: Write Only Bit 15:0 Access WO Description LEG_STS Write Port Writing a one to this register will cause the corresponding field of LEG_STS to be set. Before writing to this register, LEGPORT_EN must be set.
1
R/W
Register 5Ah~5Bh IRQ and NMI Enable for Wake-up Event Control (IRQWAK_CNT) Default Value: 0000h Access: Read/Write Bit 15:3 Access R/W Description Correspond to the enable bits for IRQ[15:3] to generate a wake-up event
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 2 1:0 R/W R/W Correspond to the enable bits for NMI to generate a wake-up event Correspond to the enable bits for IRQ[1:0] to generate a wake-up event
Register 5Ch~5Dh I/O Address Track for SMI# (ADDR_TRACK) Default Value: 0000h Access: Read Only Bit 15:0 Access RO Description I/O Address Track The reading value in this register reflects the address of last I/O cycle from CPU before the system enter SMI# handler.
Register 5Eh~5Fh I/O Command/Byte Enable Track for SMI# (CBE_TRACK) Default Value: 0000h Access: Read Only Bit 15:10 9 Access RO R/W Description Reserved I2C DATA When Register 2A[5] is selected as I2C mode, the level of pin SMBDAT is controlled by this bit. 8 R/W I2C CLOCK When Register 2A[5] is selected as I2C mode, the level of pin SMBCLK is controlled by this bit. 7:4 RO I/O Command Track The reading value in this register reflects the command of last I/O cycle from CPU before the system enter SMI# handler. 3:0 RO I/O Byte Enable Track The reading value in this register reflects the byte enable of last I/O cycle from CPU before the system enter SMI# handler. Register 60h~61h System Wakeup form S3/S4/S5 Status Register (S5WAK_STS) Default Value: 0000h Access: Read Only The following registers are all located in resume well. They can survive as long as the stanby power exists. The only way to clear the register is to write S5WAK_CLR or deassert AUXOK. Bit Access 369 Description Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 15 RO Power Button Wakeup Status (PWRBTN_S5WAK_STS) This bit will be set if power button wakes up the system from S3/S4/S5. RTC Wakeup Status (RTC_S5WAK_STS) This bit will be set if a RTC IRQ8# wakes up the system from S3/S4/S5. RING Wakeup Status (RING_S5WAK_STS) This bit will be set if RING wakes up the system from S3/S4/S5. MACPME Wakeup Status (MACPME_S5WAK_STS) This bit will be set if MAC power management event wakes up the system from S3/S4/S5. PCIPME Wakeup Status (PCIPME_S5WAK_STS) This bit will be set if PCI power management event wakes up the system from S3/S4/S5. AUDPME Wakeup Status (AUDPME_S5WAK_STS) This bit will be set if AC' 97 power management event wakes up the system from S3/S4/S5. Keyboard Password/Hotkey Wakeup Status (KBC_S5WAK_STS) This bit will be set if keyboard password or hotkey wakes up the system from S3/S4/S5. USB Wakeup Status (USB_S5WAK_STS) This bit will be set if USB wakes up the system from S3/S4/S5. SMBALT# Wakeup Status (SMBALT_S5WAK_STS) This bit will be set if SMBALT# wakes up the system from S3/S4/S5. Power Supply Resume to Previous State Status (RSM_S5WAK_STS) This bit will be set if power supply resume function wakes up the system from S5. Reserved System Suspend to DRAM State Status (S3OFF_STS) This bit will be set if the system enters to S3 state. Instant Off status (INSTOFF_STS) This bit will be set if the system is powered off due to the assertion of GPE1B2_STS. 370 Silicon Integrated Systems Corporation
14
RO
13 12
RO RO
11
RO
10
RO
9
RO
8 7
RO RO
6
RO
5:2 1 0
RO RO R/W
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 62h~63h System Wakeup form S3/S4/S5 Control Register (S5WAK_CNT) Default Value: 0000h Access: Read/Write The following registers are all located in resume well. They can survive as long as the stanby power exists. Bit 15:13 12 Access RO R/W Description Reserved AUXGPO6_EN If GPIO6 is selected as GPO6 by APC register, the assertion of this bit would make GPO6 pin alive without main power. AUXGPO5_EN If GPIO5 is selected as GPO5 by APC register, the assertion of this bit would make GPO5 pin alive without main power. AUXGPO8_EN If GPIO8 is selected as GPO8 by APC register, the assertion of this bit would make GPO8 pin alive without main power. Wake Block Counter Test Enable 0: Disable 1: Enable 7:6 RO ACPILED Output State Control The output state of ACPILED can be controlled by the following combination when system is in S0/S1/S2/S3 states. If the system is in S4/S5 state, ACPILED will be set to high impedience. 00 : Output low 01 : Blink 10 : High impedience 11 : Reversed 5:4 3 RO R/W Reserved AUXGPO6 If the GPIO6 is selected as GPO6 and AUXGPO6_EN is set, then the value of GPO6 pin would be controlled by this bit. The pin can be alive when main power disappears. AUXGPO5 If the GPIO5 is selected as GPO5 and AUXGPO5_EN is set, then the value of GPO5 pin would be controlled by this bit. The pin can be alive when main power disappears.
11
R/W
10
R/W
9:8
R/W
2
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 1 R/W AUXGPO8 If the GPIO8 is selected as GPO8 and AUXGPO8_EN is set, then the value of GPO8 pin would be controlled by this bit. The pin can be alive when main power disappears S5WAK_STS Clear Status (S5WAK_CLR) If this register is set to one, all register in S5WAK_STS will be reset to zero Reversed
0
R/W
Register 64h~7Fh
Register 80h SMBus Status (SMB_STS) Default Value: 00h Access: Read/Write Clear The following registers are all sticky bits and only can be cleared by writing a one to their corresponding fields. Bit 7 6 Access R/WC R/WC Description SMBus Slave Alert (SMBALT_STS) This bit is set when the SMBALT# is active. HIT SLAVE Alias Address (SMBALIAS_STS) This bit is set when the Host Slave received a Write Word from a device master and the address field match the Slave Alias Address register. If this bit is set to one, on more Write Word transaction can be received by SMBus Slave until this bit is cleared to zero. HIT Host Slave (SMBSLAVE_STS) This bit is set when the Host Slave received a Write Word from a device master and the address field is 10h. . If this bit is set to one, on more Write Word transaction can be received by SMBus Slave until this bit is cleared to zero. Block Array (SMBARY_STS) This bit is set when he SMBus Host has finished 8 bytes transition for Block Protocol. If the byte count of the Block protocol is 32, then total 4 Interrupt request will occur during the entire block transition. For the first three Interrupt, the service TRGine should program the following 8 data bytes as soon as possible, or the total transfer time may violate SMBus SPEC 1.0 (Timeout < 10ms). After the next eight bytes data are programmed to the SMB_BYTE0~7, the service TRGine should clear this status bit to initiate the following block transition.
5
R/WC
4
R/WC
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 3 2 R/WC R/WC Host Master (SMBMAS_STS) This bit is set when the SMBus Host Master transition is complete. SMBus Collision (SMBCOL_STS) This bit is set when a SMBus Collision condition occurs and SMBus Host loses in the bus arbitration. The software should clear this bit and re-start SMBus operation. Device Error (SMBERR_STS) This bit is set when a Device Error condition occur. The Device Errors may cause by: Host asserts an unclaimed slave address/data. Host detects a Slave Timeout-- may be a Slave error condition Slave detects a Master Timeout 0 RO SMBus Interrupt Status (SMBINTR_STS) A one in this field indicates a SMBus interrupt is generated by any of above Interrupt source.
1
R/WC
Register 81h SMBus Enable (SMB_EN) Default Value: 00h Access: Read/Write A SMBus Interrupt can be generated if Register 81h, bit 0 is enabled and the Interrupt Status bit with associated enable bits are set to one. Bit 7 Access R/W Description SMBus Slave Alert Interrupt Enable (SMBALT_EN) When this bit is enabled, a SMBus Interrupt will be generated by the active SMBALERT#. 0 : Disable 1 : Enable 6 R/W SMBus Slave Alias Address Interrupt Enable(SMBALIAS_EN) When this bit is enabled and the Device Address field of the Write Word Protocol received by Host Slave match the Slave Alias Address, a SMBus Interrupt will be generated. 0 : Disable 1 : Enable
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5 R/W SMBus Slave Interrupt Enable(SMBSLAVE_EN) When this bit is enabled and the Device Address field of the Write Word Protocol received by Host Slave is 10h, a SMBus Interrupt will be generated. 0 : Disable 1 : Enable 4 R/W Block Array Interrupt Enable (SMBARY_EN) When this bit is enabled and the Host Master has finished 8 bytes transition for Block Protocol, a SMBus Interrupt will be generated. 0 : Disable 1 : Enable 3 R/W Host Master Interrupt Enable (SMBMAS_EN) When this bit is enabled and the Host Master transition is complete, a SMBus Interrupt will be generated. 0 : Disable 1 : Enable 2 R/W SMBus Collision Interrupt Enable (SMBCOL_EN) 0 : Disable 1 : Enable Device Error Interrupt Enable (SMBERR_EN) 0 : Disable 1 : Enable SMBus Interrupt Enable (SMBINTR_EN) This bit is used to enable the SMBus interrupt generation. 0 : Disable 1 : Enable Register 82h SMBus Control (SMB_CNT) Default Value: 00h Access: Read/Write Bit 7 Access R/W Description Host Slave Timeout Enable (SLTO_EN) When this bit is enabled and the Host Slave transition time is over specification, a SMBus Interrupt will be generated. 0 : Disable 1 : Enable
1
R/W
0
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 6 R/W Host Master Timeout Enable (MSTO_EN) When this bit is enabled and the Host Master transition time is over specification, a SMBus Interrupt will be generated. 0 : Disable 1 : Enable 5 R/W SMBus Host Master Clock Selection (SMBCLK_SEL) 0 : 14KHz 1 : 56KHz Reserved Slave Busy (SL_BUSY) Indicate the Host Slave is in idle or active state. 1 : Active 0 : Idle 0 R/W Host Busy (HOST_BUSY) Indicate the Host Master is in idle or active state. When Host Master is in IDLE state, the Host Master is free for software to control. 1 : Active 0 : Idle Register 83h SMBus Host Control (SMBHOST_CNT) Default Value: 00h Access: Write Only, Read/Write Bit 7:6 5 Access RO WO Reserved Kill (SMB_Kill) This bit is set to stop all SMBus operation, including Host master and slave, all activities are set to initial state. This operation won't effect the values in R/W registers. Start (SMB_START) Writing a 1 to this bit which initiate the SMBus Host transition. The SMBus Command Protocaol bits (SMB_PTL) and the associated registers should be properly programmed before this bit is set to 1. This is a write-only bit. Reserved Description
4:2 1
RO R/W
4
WO
3
R/W
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 2:0 R/W SMBus Command Protocol (SMB_PTL) Selecting the Protocol that SMBus Host is going to execute. Reading or Writing transition is determined by SMBus Address register bit 0 (R/W bit). Bit[3:1] 000 001 010 011 100 101 110 111 Protocol Quick command Send/Receive Byte Read/Write Byte Data Read/Write Word Data Process Call Read/Write Block Data Reserved Reserved
Register 84h SMBus Address (SMB_ADDR) Default Value: 00h Access: Read/Write Bit 7:1 0 Access R/W R/W Description SMBus Address (SMB_ADDRESS) The field is the slave address to target device. SMBus Read/Write (SMB_RW) 1 : Execute a read protocol 0 : Execute a write protocol This bit doesn't effect Process Call protocol.
Register 85h SMBus Command (SMB_CMD) Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description SMBus Command (SMB_COMMAND) This register contains the command code and will be sent to device.
Register 86h SMBus Processed Byte Count (SMB_PCOUNT) Default Value: 00h Access: Read Only Bit Access 376 Description Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7:5 4:0 RO RO Reserved SMBus Processed Byte Count (SMB_PCNT) The field is the byte count that Host has transferred for block protocol. The SMBus Interrupt TRGine can read this register to know how many bytes are not transferred yet when the SMB_CNT is over 8 bytes. A ` zero' indicates a maximun of 32 data bytes has transferred.
Register 87h SMBus Byte Count (SMB_COUNT) Default Value: 00h Access: Read/Write Bit 7:5 4:0 Access RO R/W Reserved SMBus Byte Count(SMB_CNT) The field is the byte count for Block Read/Write protocol. The byte count can not be 0. Description
Register 88h~8Fh SMBus Byte0~7 (SMB_BYTE0~7) Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description SMBus Byte0~7 (SMB_BYTE0~7) These seven bytes are the data byte field for Block Read/Write protocol. The Byte0 is also used in Byte protocol, including Received Byte, Read/Write Data Byte protocol. In addition, the Byte0 (low byte) and Byte1 (high byte) are combined as word during word protocol, including Read/Write Word, Process Call protocol.
Register 90h SMBus Device Address (SMBDEV_ADDR) Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description SMBus Device Address (SMBDEV_ADDR) This field stores the Device Address when Host Slave received a Write Word protocol from other SMBus master.
Register 91h SMBus Device Byte0 (SMB_DB0) Default Value: 00h Preliminary V.10 Oct.07,1999 377 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Access: Bit 7:0 Read/Write Access R/W Description SMBus Device Byte 0 (SMB_DB0) This field stores the Data Low Byte when Host Slave received a Write Word protocol from other SMBus master.
Register 92h SMBus Device Byte1 (SMB_DB1) Default Value: 00h Access: Read/Write Bit 7:0 Access R/W Description SMBus Device Byte 1 (SMB_DB1) This field stores the Data High Byte when Host Slave received a Write Word protocol from other SMBus master.
Register 93h SMBus Host Slave Alias Address (SMB_SAA) Default Value: 00h Access: Read/Write Bit 7:1 Access R/W Description SMBus Host Slave Alias Address (SMB_ALIAS) When Host Slave receives a Device Address the same as the address in these seven bits and bit 0 is ` 0 , an interrupt will be ' raised if Alias Interrupt is also enabled. Read as ` 0 . The Host Slave accepts master Write Word protocol ' only. Reversed
0
R/W
Register 94h~9Fh
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Register Ssummary / Description - Automatic Power Control
Summary Automatic Power Control (APC) Registers
Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Name APC Register 00h APC Register 01h APC Register 02h APC Register 03h APC Register 04h APC Register 05h APC Register 06h APC Register 07h APC Register 08h Reserved
17.1
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h
Address
17.1.1 RTC Registers Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 379 Register Name Seconds Seconds Alarm Minutes Minutes Alarm Hours Hours Alarm Day of the Week Day of the Month Month Year Register A Register B ( bit 3 must be set to 0) Register C Silicon Integrated Systems Corporation
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 0Dh 7Eh 7Fh R/W R/W R/W Register D Day of the Month Alarm Month Alarm
17.2
APC Register
The following registers located at RTC power well. Before access to these registers, the APCRAM_EN must be set to one and EXPRAM_EN must be set to zero.
Register 00h CPU Frequency and Power Supply Resume Control Default Value: 04h Access: Read/Write Bit 7:4 Access R/W 0000 : 2/1 0001 : 3/1 0010 : 4/1 0011 : 5/1 3 R/W 0100 : 5/2 0101 : 7/2 0110 : 9/2 0111 : 11/2 Description Multiplication of CPU Core Frequency to Bus Frequency 1000 : 6/1 1001 : 7/1 1010 : 8/1 1011 : Rev 1100 : 13/2 1101 : 15/2 1110 : 3/2 1111 : 2/1
CPU Frequency Ratio Control Selection 0 : By Hardware Trap 1 : By bit7~4 of this register Jumperless Reset Counter Enable If CPU frequency ratio is selected as jumperless setting, the jumperless reset counter will start to count while PWROK goes active. When the counter expired, the CPU frequency ratio will be switched to hardware trap setting. 0 : Disable 1 : Enable
2
R/W
1:0
R/W
Power Supply ON/OFF State Resume Control The value in this field determines the power supply state once the standby is suddenly off. 00 : Always Off 01 : Reversed 10 : Always On 11 : Keep previous state
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Register 01h MAC and RTC Test Mode Enable Default Value: 00h Access: Read/Write Bit 7 Access R/W Description MAC Serial ROM Autoload Function Enable 0 : Disable 1 : Enable MII Test Mode Enable This bit is only for internal use. 0 : Disable 1 : Enable 5 4 R/W R/W Reserved. Warning: This bit should be set to 0. RING Input Polarity Control 0 : Active high 1 : Active low Reserved Select the frequency of the KBC This bit controls the length of the period which the KBC drives the clock line low after transmitting a byte of data. 0: SYSCLK= 8.1Khz 1: SYSCLK1=16.2Khz 1 R/W Deassert CKE_S After this bit translates to 1 from 0, a pulse would be generated to deassert CKE_S. CKE_S is used in S3 and converts the DRAM to self-refresh mode. Test Pin for KBC. When this bit is set, the clock of KBC can be inputed from GPIO3. This bit is used to test the power-on function.
6
R/W
3 2
R/W R/W
0
R/W
Register 02h Mux-ed Function Select Default Value: 00h Access: Read/Write Bit Access Description
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 7 R/W GPIO15/SMBALT# Function Select 0: GPIO15 function select 1: SMBALT# function select 6:5 R/W GPIO[14:10]/KBC Function Select 00: GPIO[14:10] function select 01: Reserved 10: KBC function select 11: Reserved 4:3 R/W GPIO8/PLED0/OC2# Function Select 00: GPIO8 function select 01: Reserved 10: OC2# function select 11: PLED0 function select 2 R/W GPIO7/SPDIF Select 0: GPIO7 function select 1: SPDIF test function select 1 R/W GPIO[6:4] Select 0: GPIO[6:4] function select 1: Reserved 0 R/W GPIO3/EEDO Function Select 0: GPIO3 function select 1: EEDO function select Register 03h Mux-ed Function Select Default Value: 00h Access: Read/Write 7:6 R/W GPIO2/LDRQ#/OC3# Function Select 00: GPIO2 function select 01: Reserved 10: OC3# 11: LDRQ# function select
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5:4 R/W GPIO[1:0]/OC[1:0]/PCI Master Function Select 00: GPIO[1:0] function select 01: Reserved 10: OC[1:0] 11: PCI Master function select 3 R/W USB Test Function Enable 0: Disable 1: Enable 2 R/W Keyboard ROM Data Test Function Enable 0: Disable 1: Enable 1:0 R/W MII Operation Mode Select 00: Normal mode 01: Probe mode 10: MAC test mode 11: PHY test mode Register 04h System Power-Off Control Default Value: 00h Access: Read/Write Bit 7:3 2 Access R/W R/W Description Reserved USB Plug-in/Pluck-out Wake up from S3/S4/S5 If this bit and the corresponding bit in APC6h are set, the system will be powered due to the " plug-in/pluck-out" action of the usb device. ACPI S5 Function Enable (S5OFF_EN) 0 : Disable 1 : Enable ACPI S3 Function Enable (S3OFF_EN) 0 : Disable 1 : Enable
1
R/W
0
R/W
Register 05h GPE Wakeup Enable Default Value: 00h Preliminary V.10 Oct.07,1999 383 Silicon Integrated Systems Corporation
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Access: Bit 7 Read/Write Access R/W Description RTC IRQ8 Wake from S3/S4/S5 Enable (RTC_S5WAK_EN) 0 : Disable 1 : Enable RING Wake from S3/S4/S5 Enable (RING_S5WAK_EN) 0 : Disable 1 : Enable MACPME Wake from S3/S4/S5 Enable (MACPME_S5WAK_EN) 0 : Disable 1 : Enable PCIPME Wake from S3/S4/S5 Enable (PCIPME_S5WAK_EN) 0 : Disable 1 : Enable SMBALT# Wake from S3/S4/S5 Enable (SMBALT_S5WAK_EN) 0 : Disable 1 : Enable Keyboard Password (KBPS_S5WAK_EN) 0 : Disable 1 : Enable Keyboard Hotkey (KBHK_S5WAK_EN) 0 : Disable 1 : Enable Wake from S3/S4/S5 Enable
6
R/W
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
Wake
from
S3/S4/S5
Enable
0
R/W
Keyboard 8MHz Clock Shutdown Switch the enable bit of the KBC internal 8Mhz clock generator. 0 : Clock Running 1 : Clock shutdown
Register 06h Audio and USB Wakeup Enable Default Value: 00h Access: Read/Write Bit 7 Access R/W Description CODEC1 Wake from S3/S4/S5 Enable (CODEC1_S5WAK_EN) 0 : Disable 1 : Enable 384 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 6 R/W CODEC0 Wake from S3/S4/S5 Enable (CODEC0_S5WAK_EN) 0 : Disable 1 : Enable AUDPME Wake from S3/S4/S5 Enable (AUDPME_S5WAK_EN) 0 : Disable 1 : Enable USB Port4 Wake from S3/S4/S5 Enable (USB4_S5WAK_EN) 0 : Disable 1 : Enable USB Port3 Wake from S3/S4/S5 Enable (USB3_S5WAK_EN) 0 : Disable 1 : Enable USB Port2 Wake from S3/S4/S5 Enable (USB2_S5WAK_EN) 0 : Disable 1 : Enable USB Port1 Wake from S3/S4/S5 Enable (USB1_S5WAK_EN) 0 : Disable 1 : Enable USB Port0 Wake from S3/S4/S5 Enable (USB0_S5WAK_EN) 0 : Disable 1 : Enable
5
R/W
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
Register 07h The Parameters of RTC Oscillator Default Value: 00h Access: Read/Write The following registers are used to modulate the oscillator. The detailed description can be found in another application Note. 7:4 3:0 R/W R/W Cout[3:0] These four bits are used to modulate the oscillator capacity. Cin[3:0] These four bits are used to modulate the oscillator capacity.
Register 08h The Parameters of RTC Oscillator Default Value: 00h Access: Read/Write 7:6 R/W Reserved. 385 Silicon Integrated Systems Corporation
Preliminary V.10 Oct.07,1999
SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset 5:3 2 1 0 R/W R/W R/W R/W SR[2:0] for oscillator. OSCSEL OSC ATE OSCPROBEN.
Register 09h Default Value: 00h Access: Read/Write 7:0 R/W Reserved.
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18.1
Electrical Characteristics
Absolute maximum Ratings
Table 18.1-1 Absolute Maximum Ratings
Parameter Ambient operation temperature Storage temperature Input voltage Output voltage
Min. 0 -40 -0.3 -0.5 70 125
Max.
0 0
Unit C C
Vcc+0.3 Vcc
V V
NOTE: Stress above these listed may cause permanent damage to device. Functional operation of this device should be restricted to the conditions described under operating conditions.
18.2
DC Characteristics
18.2.1 DC Characteristics Ta=0-700C, Gnd=0V, Vcc3=3.3V5%, vcc18=1.8V5%,VTT = 1.5v10%, Table18.2-1 DC Characteristics of Host, DRAM, PCI and IDE Interface Symbol VIH_GTL VIL_GTL VIH_TTL VIL_TTL VIH_ VIL VOL_GTL VOL_TTL VREF IOL_GTL IOH_TTL Parameter GTL+ Input High Voltage GTL+ Input High Voltage TTL Input High Voltage TTL Input Low Voltage RTC Input High Voltage RTC Input Low Voltage GTL+ Output Low Voltage TTL Output Low Voltage GTL+ Reference Voltage GTL+ Output Low Current TTL Output High Current -4 387 2/3VTT 2% 2 -0.3 1.4 -0.3 Min 2/3VTT +0.2 2/3VTT 0.2 VCC3+0. 3 0.8 VCC18+0 .3 0.4 0.6 0.45 2/3VTT+2 % 36 Max V V V V V V V V V mA mA Silicon Integrated Systems Corporation Unit Notes
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset IOL_TTL IIL TTL Output Low Current Input Leakage Current 4 10 mA mA
18.2.2 DC Characteristics for DAC (Analog Output Characteristics)
Table 18.2-1 Table of DC Characteristics for DAC Description Black Level White Level ILE DLE 1 LSB Iref Min -1.0 -0.5 Typical 0 700 2.734 8.40 Max +1.0 +0.5 Unit V mV LSB LSB mV mA
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Mechanical Dimension
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Power Sequence in SIS630
If the system doesn't support AUXVDD, AUXOK must be connected with PWROK. There is no well-defined sequence for RTCVDD, AUXVDD, and VDD. Note that AUXOK and PWROK signal pins are powered by RTCVDD. These two pins must have their own pull-down resistors to prevent them from floating if AUXVDD or VDD is not presented. In SIS630, BATOK is used to reset some power management registers in RTC power plane. If it goes low, all registers in RTC power plane will be reset. By the time of next booting up, the BIOS will shows "CMOS Checksum Fail" to indicate that the RTCVDD had been absent. AUXOK is used to reset the power management registers in AUX power plane. If AUXOK goes low for some reason, the registers in AUX power plane will be reset to their default state. If the system is in power-off state, only PWRBTN# can power up the system under this circumstance. If the system is ON and AUXOK go low for some strange reason, the power will be shutdown immediately. Finally, PWROK is used to generate CPURST# and PCIRST#. If this signal is de-asserted, PCIRST# and CPURST# will be asserted and the system will be reset by these two reset signal. Note that CPURST# and PCIRST# won't reset the registers which locate in RTC and AUX power planes.
t1 RTCVDD BATOK AUXVDD AUXOK VDD PWROK
t2
t3
Plug Power Cord
Power On
T1 > 1ms T2 > 10ms T3 > 100ms
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20.1
630 Package on 4 Layer PCB
630A Temp vs Power (With Heat Sink )
80 70
Temp (C)
60 50 40 30 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Power (W)
Tcase Tbutton
Condition : Room Temperature 30C (Still air) With 38mm*38mm Aluminum Heat Sink Theda ja 13.8 C/W Maximum Power Dissipation = 4.3W Tcase : Temperature at the of molding compound Surface Tbutton : Temperature at the back side of PCB where thermal balls are directly attached
20.2
630 Package on 4 Layer PCB
Without Heat Sink
Condition : Room Temperature 30C (Still air)
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SIS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset Figure 20.2-1 630 A Temp vs Power(2)
630A Temp vs Power (Without Heat Sink )
80 70
Temp (C)
60 50 40 30 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
Power (W)
Tcase Tbutton
Theda ja 17.7 C/W Maximum Power Dissipation =3.4W Tcase : Temperature at the of molding compound Surface Tbutton : Temperature at the back side of PCB where thermal balls are directly attached
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Copyright Notice
Copyright 1999, Silicon Integrated Systems Corp. All rights reserved. This manual is copyrighted by Silicon Integrated Systems Corp. You may not reproduce, transmit, transcribe, store in a retrieval system, or translate into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, any part of this publication without the expressly written permission from Silicon Integrated Systems Corp. Trademarks SiS is a registered trademark of Silicon Integrated Systems Corp. All brand or product names mentioned are trademarks or registered trademarks of their respective holders. Disclaimer Silicon Integrated Systems Corp. makes no representations or warranties regarding the contents of this manual. We reserve the right to revise the manual or make changes in the specifications of the product described within it at any time without notice and without obligation to notify any person of such revision or change. The information contained in this manual is provided for the general use by our customers. Our customers should be aware that the personal computer field is the subject of many patents. Our customers should ensure that they take appropriate action so that their use of our products does not infringe upon any patents. It is the policy of Silicon Integrated Systems Corp. To respect the valid patent rights of third parties and not to infringe upon or assist others to infringe upon such rights. Restricted Rights Legend Use, duplication, or disclosure by the Government is subject to restrictions set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at 252.277-701
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